A circuit includes a plurality of scan chains arranged in a ring network topology. Each scan chain includes a plurality of scan blocks, each of the plurality of scan blocks including a storage element and a switching device. Each switching device includes a first input configured to receive an output of a storage element in a different scan chain from the scan chain in which the switching device is disposed, and a second input configured to receive one of a function logic signal or a test scan signal. The switching device configured to selectively couple the first input or the second input to an input of the storage element.

A data storage apparatus is provided which has a plurality of data storage units, each respective data storage unit configured to store a respective data bit of a data word. Stored data value parity generation circuitry is configured to generate a parity bit for the data word in dependence on the data bits of the data word stored in the plurality of data storage units. The stored data value parity generation circuitry is configured such that switching within the stored data value parity generation circuitry does not occur when the data word is read out from the plurality of data storage units. Transition detection circuitry is configured to detect a change in value of the parity bit.

A system and method are provided on one or more companion chips having a plurality of cores. Each core has core circuitry and a test interface for carrying out tests in relation to the core circuitry. The test interface has an address register to hold an address of the core and address determination circuitry. The address determination circuitry is configured to compare an address received on an address line to the address held in the address register to determine whether a core is being addressed. The address determination circuitry is also configured to direct the test interface to carry out a testing operation in response to the determination.

Resetting an integrated circuit (IC) by reset circuit of the IC comprises receiving a clock signal and a data signal. A sequence of bits of the data signal is stored in a memory based on the clock signal. A test mode signal is received and the sequence of bits is decoded in response to receiving the test mode signal. One of adjusting a counter value of a counter of the reset circuitry and outputting a reset signal corresponding to the counter value is performed based on the decoded sequence of bits.

A circuit includes a plurality of scan chains arranged in a ring network topology. Each scan chain includes a plurality of scan blocks, each of the plurality of scan blocks including a storage element and a switching device. Each switching device includes a first input configured to receive an output of a storage element in a different scan chain from the scan chain in which the switching device is disposed, and a second input configured to receive one of a function logic signal or a test scan signal. The switching device configured to selectively couple the first input or the second input to an input of the storage element.

Embodiments relate to systems and methods for defect detection and localization in semiconductor chips. In an embodiment, a plurality of registers is arranged in a semiconductor chip. The particular number of registers can vary according to a desired level of localization, and the plurality of registers are geometrically distributed such that defect detection and localization over the entire chip area or a desired chip area, such as a central active region, is achieved in embodiments. In operation, a defect detection and localization routine can be run in parallel with other normal chip functions during a power-up or other phase. In embodiments, the registers can be multi-functional in that they can be used for other operational functions of the chip when not used for defect detection and localization, and vice-versa. Embodiments thereby provide fast, localized defect detection.

Testing an integrated circuit (IC) that has a set of nominally similar cores and pairs of test data input (TDI) and test data output (TDO) pads common to the different cores. Similar scan chains in parallel in the different cores provide response signals as functions of corresponding TDI signals. Respective combined TDO signals are provided to the TDO pads. In the absence of a defect, the combined TDO signals are asserted and de-asserted like the response signals from corresponding chains in the different cores and like corresponding expected response signals. The combined TDO signals are different from the corresponding expected response signals in the presence of a defect in at least one of the cores. If the result is a fail, the ATE may identify a defective core using a diagnosis module in the IC providing response signals from a selected core.

The JTAG debug apparatus includes: a TAP controller, configured to communicate with outside by using an external JTAG port, and generate, based on a signal received from the JTAG port, a debug signal including an address of the to-be-debugged unit and a debug instruction, where the debug signal is a JTAG port signal based on the JTAG protocol; a signal conversion unit, configured to receive the debug signal that is output from the TAP controller, and convert the debug signal from the JTAG port signal to a bus slave port signal that can access a slave port of the to-be-debugged unit; and a bus, configured to obtain the debug signal that is converted to the bus slave port signal and that is output from the signal conversion unit, and transmit, based on the debug signal, the debug instruction to the to-be-debugged unit indicated by the address of the to-be-debugged unit.

A test apparatus for generating reference scan chain test data comprises a test pattern generator and an output data modifier. The test pattern generator modifies a scan chain test input bit sequence by replacing a predefined number of start bits of the scan chain test input bit sequence by a predefined start bit sequence. Further, the test pattern generator provides the modified scan chain test input bit sequence to a device under test. The output data modifier modifies a scan chain test output bit sequence received from the device under test and caused by the modified scan chain test input bit sequence. The scan chain test output bit sequence is modified by replacing a predefined number of end bits of the scan chain test output bit sequence by a predefined end bit sequence to obtain the reference scan chain test data.

A circuit includes a plurality of scan chains arranged in a ring network topology. Each scan chain includes a plurality of scan blocks, each of the plurality of scan blocks including a storage element and a switching device. Each switching device includes a first input configured to receive an output of a storage element in a different scan chain from the scan chain in which the switching device is disposed, and a second input configured to receive one of a function logic signal or a test scan signal. The switching device configured to selectively couple the first input or the second input to an input of the storage element.