A method is provided in the present disclosure. The method includes several operations: generating, by a processing unit, a mapping table associated with multiple scan chains and multiple shift cycles corresponding to multiple values stored in the scan chains in an integrated circuit; determining, based on the mapping table, at least one fail flip flop in the scan chains in response to the values outputted from the scan chains; and identifying at least one fault site corresponding to the at least one fail flip flop.

A semiconductor device addresses to a problem in which a current consumption variation rate increases during BIST execution causing resonance noise generation in a power supply line. The semiconductor device includes a self-diagnosis control circuit, a scan target circuit including a combinational circuit and a scan flip-flop, and an electrically rewritable non-volatile memory. A scan chain is configured by coupling a plurality of the scan flip-flops. In accordance with parameters stored in the non-volatile memory, the self-diagnosis control circuit can change a length of at least one of a scan-in period, a scan-out period and a capture period, and can also change a scan start timing.

Provided are scan device and method of diagnosing scan chain fault. The scan device for diagnosing a fault includes a scan partition including a plurality of scan chains which include path control scan flipflops connected to scan flipflops in cascade. In the scan partition, connection paths of the scan flipflops are controllable. The connection paths of the path control scan flipflops are controlled to detect a position of a fault such that a fault range in the scan partition is reduced to diagnose the fault.

An error rate measuring apparatus that inputs a PAM4 signal of a known pattern as a test signal to a device under test W, receives a signal from the device under test W compliant with the input of the test signal, and measures whether or not an FEC operation of the device under test W is possible based on a comparison result of the received signal and the test signal includes an operation unit that sets one Codeword length and one FEC Symbol length of the FEC as a setting parameter to the signal received from the device under test W according to a communication standard of the device under test W, and a display unit that parallel-displays MSB data and LSB data of each piece of symbol string data obtained by receiving and converting the signal from the device under test W on a display screen.

A boundary scan test method and a storage medium are disclosed. The method can be capable of testing the connectivity of a pad having a direct connection to user logic. The method is preformed based on a scan test instruction to FPGA. According to the method of the invention, software configuration is performed in FPGA user logic with respect to a PAD to be tested, such that the PAD can be tested according to the configuration without the need to test or pass through PADs that do not need to be tested. The method shortens boundary scan chains, thereby enabling rapid and flexible boundary scan tests and improving test efficiency.

A method is provided and includes several operations: testing multiple scan chains in multiple shift cycles to obtain multiple values; determining at least one fail chain in the scan chains and determining at least one fail shift cycle corresponding to at least one fail value in the values; mapping the at least one fail chain and the at least one fail shift cycle to the scan chains to identify the at least one fail flip flop; and identifying at least one fault site corresponding to the at least one fail flip flop.

Embodiments are directed to a computer implemented method and system for the testing, characterization and diagnostics of integrated circuits. A system might include a device under test, such as an integrated circuit, that includes an adaptive microcontroller. The method includes loading a testing program for execution by the adaptive microcontroller, causing the microcontroller to execute the testing program. Once results from the testing program are received, the testing program can be adaptively modified based on the results. The modified testing program can be run again. The testing program can modify parameters of the integrated circuit that are not externally accessible. Other embodiments are also disclosed.

A semiconductor device addresses to a problem in which a current consumption variation rate increases during BIST execution causing resonance noise generation in a power supply line. The semiconductor device includes a self-diagnosis control circuit, a scan target circuit including a combinational circuit and a scan flip-flop, and an electrically rewritable non-volatile memory. A scan chain is configured by coupling a plurality of the scan flip-flops. In accordance with parameters stored in the non-volatile memory, the self-diagnosis control circuit can change a length of at least one of a scan-in period, a scan-out period and a capture period, and can also change a scan start timing.

A method includes disconnecting a data bus connecting a test access port (TAP) controller of an integrated circuit (IC) chip to a plurality of test data registers deployed on the chip, simultaneously supplying test data to multiple test data registers among the plurality of test data registers, and storing test response data, received from the plurality of test data registers and responsive to the test data, in storage registers deployed on the chip.

A method is provided in the present disclosure. The method includes several operations: generating, by a processing unit, a mapping table associated with multiple scan chains and multiple shift cycles corresponding to multiple values stored in the scan chains in an integrated circuit; determining, based on the mapping table, at least one fail flip flop in the scan chains in response to the values outputted from the scan chains; and identifying at least one fault site corresponding to the at least one fail flip flop.