A semiconductor integrated circuit includes scan chains, each of which includes a serial connection of sequential circuits and performs a shift register operation in a scan test; and an integrated clock gating (ICG) chain composed by coupling, to one another, ICG circuits, each of which individually supplies a corresponding one of the scan chains with a circuit clock signal to operate the sequential circuits. In the ICG chain, an ICG enable propagation signal for controlling timing when the ICG circuits output the circuit clock signals propagates through a signal line and is input sequentially to the ICG circuits. The ICG circuits output the circuit clock signals at respective timings that are different among the scan chains.

In an embodiment, a method for performing scan includes: entering scan mode; receiving a test pattern; applying the test pattern through a first scan chain by asserting and deasserting a scan enable signal to respectively perform shift and capture operations to the first scan chain; while applying the test pattern through the first scan chain, controlling a further scan flip-flop with the first scan chain without transitioning a further scan enable input of the further scan flip-flop; and evaluating an output of the first scan chain to detect faults.

In an embodiment, a method for performing scan includes: entering scan mode; receiving a test pattern; applying the test pattern through a first scan chain by asserting and deasserting a scan enable signal to respectively perform shift and capture operations to the first scan chain; while applying the test pattern through the first scan chain, controlling a further scan flip-flop with the first scan chain without transitioning a further scan enable input of the further scan flip-flop; and evaluating an output of the first scan chain to detect faults.

Testing of integrated circuitry, wherein the integrated circuitry includes a flip-flop with an asynchronous input, so that during performance of asynchronous scan patterns, glitches are avoided. Combinatorial logic circuitry delivers a local reset signal to the asynchronous input independent of an assertion of an asynchronous global reset signal. A synchronous scan test is performed of delivery of the local reset signal from the combinatorial logic circuitry while masking delivery of any reset signal to the asynchronous input of the flip-flop. An asynchronous scan test is performed of an asynchronous reset of the flip-flop with the asynchronous global reset signal while masking delivery of the local reset signal to the asynchronous input of the flip-flop.

A semiconductor integrated circuit includes: scan chains each of which includes a serial connection of sequential circuits and performs a shift register operation in a scan test; and an ICG chain composed by coupling, to one another, ICG circuits each of which individually supplies any of the scan chains with a circuit clock signal for operating the sequential circuits. In the ICG chain, an ICG enable propagation signal for controlling timing when the ICG circuits output the circuit clock signals propagates through a signal line and is input sequentially to the ICG circuits. The ICG circuits output the circuit clock signals at pieces of timing which are different between the scan chains.

A family of novel, low power, min-drive strength, double-edge triggered (DET) input data multiplexer (Mux-D) scan flip-flop (FF) is provided. The flip-flop takes the advantage of no state node in the slave to remove data inverters in a traditional DET FF to save power, without affecting the flip-flop functionality under coupling/glitch scenarios.

Testing of integrated circuitry, wherein the integrated circuitry includes a flip-flop with an asynchronous input, so that during performance of asynchronous scan patterns, glitches are avoided. Combinatorial logic circuitry delivers a local reset signal to the asynchronous input independent of an assertion of an asynchronous global reset signal. A synchronous scan test is performed of delivery of the local reset signal from the combinatorial logic circuitry while masking delivery of any reset signal to the asynchronous input of the flip-flop. An asynchronous scan test is performed of an asynchronous reset of the flip-flop with the asynchronous global reset signal while masking delivery of the local reset signal to the asynchronous input of the flip-flop.

The present disclosure provides a testing method and a testing system. The testing method is performed by at least one processor and includes the following operations: converting a circuit data of a scan test to a program, in which the program is configured to observe an untested part of a circuitry that is unable to be tested in the scan test; generating a waveform data associated with the untested part; generating a look-up table according to the program and a netlist file, in which the netlist file indicates the circuitry; and testing the untested part of the circuitry according to the waveform data and the look-up table.

A family of novel, low power, min-drive strength, double-edge triggered (DET) input data multiplexer (Mux-D) scan flip-flop (FF) is provided. The flip-flop takes the advantage of no state node in the slave to remove data inverters in a traditional DET FF to save power, without affecting the flip-flop functionality under coupling/glitch scenarios.

The present disclosure provides a testing method and a testing system. The testing method is performed by at least one processor and includes the following operations: converting a circuit data of a scan test to a program, in which the program is configured to observe an untested part of a circuitry that is unable to be tested in the scan test; generating a waveform data associated with the untested part; generating a look-up table according to the program and a netlist file, in which the netlist file indicates the circuitry; and testing the untested part of the circuitry according to the waveform data and the look-up table.