A mask data generation method including: calculating first evaluation value of projection image based on first mask data in which first value or second value different from first value is set for each of a plurality of unit elements that constitute 2-dimensional grid; generating second mask data by changing value of first unit element to which first value is set to second value and by changing value of second unit element which is disposed close to first unit element on 2-dimensional grid and to which second value is set to first value, among the plurality of unit elements included in the first mask data; calculating second evaluation value of projection image based on the second mask data; and comparing the first evaluation value and the second evaluation value and selecting either the first mask data or the second mask data as output mask data based on the comparison result.

In embodiments of a digital lithography system, physical design data prepared at a data prep server in a hierarchical data structure. A leaf node comprises a repeater nod, comprising a bitmap image and a plurality of locations at which the bitmap appears in a physical design. At an EYE server, a repeater node bitmap is adjusted based upon, for example, spatial light modulator rotational adjustment and substrate distortion. The adjusted repeater node and the plurality of locations in which the adjusted repeater appears is compared to the repeater of the data prep server and its plurality of locations. In further embodiments, a rasterizer generates a checksum of bitmap to be printed to a substrate, from the EYE server bitmap. The checksum is compared to a checksum of the EYE server bitmap.

Systems and methods disclosed are generally related to masklessly developing connections between a chip-group and a design connection point on a substrate. In placement of the chip-group on the substrate, according to certain embodiments the chip-group may be dispositioned relative to an expected position per a substrate layout design, causing a connection misalignment with the design connection point. According to certain embodiments, a machine learning (ML) model is trained on historical and simulated pixel models of chip-group connections and design connection points. Upon determining the chip-group misalignment by a metrology measurement, the trained ML model determines a pixel model to connect the misaligned chip-group, and causes the pixel model to be exposed to a substrate with a digital lithography tool, thereby connecting the dispositioned chip-group to the design connection point.

Embodiments disclosed herein relate to an exposure pattern alteration software application which manipulates exposure polygons having lines with angles substantially close to angles of symmetry of a hex close pack arrangement, which suffer from long jogs. Long jogs present themselves as high edge placement error regions. As such, the exposure pattern alteration software application provides for line wave reduction by serrating polygon edges at affected angles to reduce edge placement errors during maskless lithography patterning in a manufacturing process.

Conventional optical lithography uses masks with static patterns that are expensive and labor intensive to produce. The present disclosure is directed to a programmable optical lithography mask with an array of cells that use a hydrogen-mediated mechanism to tune their optical properties (e.g., transmission, absorption, refractive index, and/or reflectivity) dynamically and reversibly. Each cell in the programmable mask may be individually addressable to produce a large variety of patterns. The programmable mask may be configured for ultra-fine spatial resolution or coarse spatial resolution, facilitating a wide range of applications. The programmable mask may be stable against short wavelength light, such as broadband ultraviolet (UV) light, and can thus act as a light valve for short wavelength light.

The present disclosure relates to apparatus and methods for performing maskless lithography processes. A substrate rocessing apparatus includes a slab with a plurality of guiderails coupled to and extending along the slab. A first shuttle is disposed on the plurality of guiderails, a second shuttle is disposed on the first shuttle, and a metrology bar is coupled to the second shuttle. The etrology bar includes a first plurality of sensors coupled to the metrology bar. A second plurality of sensors coupled to the metrology bar are disposed laterally inward of the first plurality of sensors.

A control method for a spatial light modulator for an exposure apparatus having a projection optical system having an optical elements a state of each of which is allowed to be changed, the method sets states of optical elements located in a first area to a first distribution in which a first optical element in a first state and a second optical element in a second state are distributed in a first distribution pattern so that one portion of a light from the optical elements located in the first area enters the projection optical system and setting states of optical elements located in a second area to a second distribution in which the first optical element and the second optical element are distributed in a second distribution pattern to reduce a deterioration of the pattern image caused by a light that enters the projection optical system from the first area.

Embodiments of the present disclosure relate to a system, a software application, and a method of a lithography process to update one or more of a mask pattern, maskless lithography device parameters, lithography process parameters utilizing a file readable by each of the components of a lithography environment. The file readable by each of the components of a lithography environment stores and shares textual data and facilitates communication between of the components of a lithography environment such that the mask pattern corresponds to a pattern to be written is updated, the maskless lithography device of the lithography environment is calibrated, and process parameters of the lithography process are corrected for accurate writing of the mask pattern on successive substrates.

Embodiments of the present disclosure include a lithography apparatus, patterning system, and method of patterning a layered structure. The patterning system includes an image formation device and a reactive layer. The patterning system allows for creating lithography patterns in a single operation. The lithography apparatus includes the patterning system and an optical system. The lithography apparatus uses a plurality of wavelengths of light, along with the image formation device, to create a plurality of color patterns on the reactive layer. The method of patterning includes exposing the reactive layer to a plurality of wavelengths of light. The light reacts differently with different regions of the reactive layer, depending on the wavelength of light emitted onto the different regions. The method and apparatuses disclosed herein require only one image formation device and one lithography operation.

A verification device for verifying a design file for digital lithography comprises a memory and a controller. The memory comprises the design file. The controller is configured to access the design file and apply one or more compliance rules to the design file to determine compliance of the design file. The compliance rules comprises at least one of detecting non-orthogonal edges within the design file, detecting non-compliant overlapping structures within the design file, and detecting a non-compliant interaction between a reference layer of the design file and a target layer of the design file. The controller is further configured to verify the design file in response to a comparison of a number of non-orthogonal edges, non-compliant overlapping structures and non-compliant interactions to a threshold.