A method of generating a layout pattern includes determining a first energy density indirectly exposed to a first feature of one or more features of a layout pattern on an energy-sensitive material when the one or more features of the layout pattern on the energy-sensitive material are directly exposed by a charged particle beam. The method also includes adjusting a second energy density exposed the first feature when the first feature is directly exposed by the charged particle beam. A total energy density of the first feature that comprises a sum of the first energy density from the indirect exposure and the second energy density from the direct exposure is maintained at about a threshold energy level to fully expose the first feature in the energy-sensitive material.

Systems and methods disclosed are generally related to masklessly developing connections between a chip-group and a design connection point on a substrate. In placement of the chip-group on the substrate, according to certain embodiments the chip-group may be dispositioned relative to an expected position per a substrate layout design, causing a connection misalignment with the design connection point. According to certain embodiments, a machine learning (ML) model is trained on historical and simulated pixel models of chip-group connections and design connection points. Upon determining the chip-group misalignment by a metrology measurement, the trained ML model determines a pixel model to connect the misaligned chip-group, and causes the pixel model to be exposed to a substrate with a digital lithography tool, thereby connecting the dispositioned chip-group to the design connection point.

Embodiments disclosed herein relate to an exposure pattern alteration software application which manipulates exposure polygons having lines with angles substantially close to angles of symmetry of a hex close pack arrangement, which suffer from long jogs. Long jogs present themselves as high edge placement error regions. As such, the exposure pattern alteration software application provides for line wave reduction by serrating polygon edges at affected angles to reduce edge placement errors during maskless lithography patterning in a manufacturing process.

A method to improve a lithographic process of imaging a portion of a design layout onto a substrate using a lithographic projection apparatus, the method including: computing a multi-variable cost function, the multi-variable cost function being a function of a stochastic variation of a characteristic of an aerial image or a resist image, or a function of a variable that is a function of the stochastic variation or that affects the stochastic variation, the stochastic variation being a function of a plurality of design variables that represent characteristics of the lithographic process; and reconfiguring one or more of the characteristics of the lithographic process by adjusting one or more of the design variables until a certain termination condition is satisfied.

An electronic device includes a substrate having contact pads disposed thereon and traces interconnecting the contact pads. A first integrated circuit (IC) die is mounted on the substrate and includes a predefined set of circuit components arranged on the first IC die in a first geometrical pattern, which is non-symmetrical under reflection about a given axis in a plane of the die. A second IC die is mounted on the substrate and includes the predefined set of circuit components arranged on the second IC die in a second geometrical pattern, which is a mirror image of the first geometrical pattern with respect to the given axis.

Pattern centric process control is disclosed. A layout of a semiconductor chip is decomposed into a plurality of intended circuit layout patterns. For the plurality of intended circuit layout patterns, a corresponding plurality of sets of fabrication risk assessments corresponding to respective ones of a plurality of sources is determined. Determining a set of fabrication risk assessments for an intended circuit layout pattern comprises determining fabrication risk assessments based at least in part on: simulation of the intended circuit layout pattern, statistical analysis of the intended circuit layout pattern, and evaluation of empirical data associated with a printed circuit layout pattern. A scoring formula is applied based at least in part on the sets of fabrication risk assessments to obtain a plurality of overall fabrication risk assessments for respective ones of the plurality of intended circuit layout patterns. The plurality of intended circuit layout patterns is ranked based on their fabrication risk assessments, the corresponding overall fabrication risk assessments, or both. At least a portion of ranking information is outputted to facilitate influence or control over the semiconductor fabrication process.

A photolithographic exposure method for a memory. In a photolithographic process for making a memory, when exposure is performed by using a mask, regions with different exposure dimension requirements on the memory are divided into different exposure groups. Regions with the same exposure resolution requirement are divided into the same group. Different exposure modes of exposure that are capable of correspondingly satisfying resolution requirements of each group are performed to different groups during exposure. During exposure, different illumination modes are adopted to perform exposure. Firstly, a first exposure mode is adopted to perform exposure to a memory array cell exposure group, then a wafer is kept stationary on a supporting platform, and then a second exposure mode is adopted to perform exposure to the other structure exposure group; after the exposure of all groups is completed, one-step development is performed to complete pattern transfer.

A method for source mask optimization or mask only optimization used to image a pattern onto a substrate. The method includes determining a non-uniform illumination intensity profile for illumination; and determining one or more adjustments for the pattern based on the non-uniform illumination intensity profile until a determination that features patterned onto a substrate substantially match a target design. The non-uniform illumination intensity profile may be determined based on an illumination optical system and projection optics of a lithographic apparatus. In some embodiments, the lithographic apparatus includes a slit, and the non-uniform illumination profile is a through slit non-uniform illumination intensity profile. Determining the one or more adjustments for the pattern may include performing optical proximity correction, for example.

An extreme ultraviolet lithography (EUVL) method includes providing at least two phase-shifting mask areas having a same pattern. A resist layer is formed over a substrate. An optimum exposure dose of the resist layer is determined, and a latent image is formed on a same area of the resist layer by a multiple exposure process. The multiple exposure process includes a plurality of exposure processes and each of the plurality of exposure processes uses a different phase-shifting mask area from the at least two phase-shifting mask areas having a same pattern.

A digital pattern generation system comprises a memory and a controller. The controller is coupled the memory and is configured to remove redundant cells from a digital pattern file, generate a first updated digital pattern file and compare the first updated digital pattern file with the digital pattern file. Further a number of vertexes of a first arc of the first updated digital pattern file is reduced to generate a second updated digital pattern file. Additionally, a first cell of the second updated digital pattern file is replaced with an alternative version of the first cell to generate a third updated digital pattern file. Further, one or more polygons within the third updated digital pattern file is converted to one or more quad polygons to generate an optimized digital pattern file.