A method of forming sub-resolution features that includes: exposing a photoresist layer formed over a substrate to a first ultraviolet light (UV) radiation having a first wavelength of 365 nm or longer through a mask configured to form features at a first critical dimension, the photoresist layer including first portions exposed to the first UV radiation and second portions unexposed to the first UV radiation after exposing with the first UV radiation; exposing the first portions and the second portions to a second UV radiation; and developing the photoresist layer after exposing the photoresist layer to the second UV radiation to form the sub-resolution features having a second critical dimension less than the first critical dimension.

In a method of manufacturing a photo mask used in a semiconductor manufacturing process, a mask pattern layout in which a plurality of patterns are arranged is acquired. The plurality of patterns are converted into a graph having nodes and links. It is determined whether the nodes are colorable by N colors without causing adjacent nodes connected by a link to be colored by a same color, where N is an integer equal to or more than 3. When it is determined that the nodes are colorable by N colors, the nodes are colored with the N colors. The plurality of patterns are classified into N groups based on the N colored nodes. The N groups are assigned to N photo masks. N data sets for the N photo masks are output.

A method for manufacturing a plurality of mechanical resonators (100) in a manufacturing wafer (10), the resonators being intended to be fitted to an adjusting member of a timepiece, the method comprising the following steps: (a) manufacturing a plurality of resonators in at least one reference wafer according to reference specifications, such manufacture comprising at least one lithography step to form patterns of the resonators on or above the reference wafer and a step of machining in the reference plate using the patterns; (b) for the at least one reference plate, establishing a map indicative of the dispersion of stiffnesses of the resonators relative to an average stiffness value; (c) dividing the map into fields and determining a correction to be made to the dimensions of the resonators for at least one of the fields in order to reduce the dispersion; (d) modifying the reference specifications for the lithography step so as to make the corrections to the dimensions for the at least one field in the lithography step; (e) manufacturing resonators in a manufacturing wafer using the modified specifications.

A method for forming ultra-high density integrated circuitry, such as for a 6T SRAM, for example, is provided. The method involves applying double patterning litho-etch litho-etch (LELE) and using a spacer process to shrink the critical dimension of features. To improve process margins, the method implements a double-patterning technique by modifying the layout and splitting cross-coupling straps into two colors (e.g., each color corresponds to a mask-etch process). In addition, a spacer process is implemented to shrink feature size and increase the metal-to-metal spacing between the two cross-coupling straps, in order to improve process margin and electrical performance. This is achieved by depositing a spacer layer over an opening in a hardmask, followed by spacer etch back. The opening is thus shrunk by the amount of spacer thickness. The strap-to-strap spacing may then be increased by twice the amount of spacer thickness.

The present disclosure relates a lithographic substrate marking tool. The tool includes a first electromagnetic radiation source disposed within a housing and configured to generate a first type of electromagnetic radiation. A radiation guide is configured to provide the first type of electromagnetic radiation to a photosensitive material over a substrate. A second electromagnetic radiation source is disposed within the housing and is configured to generate a second type of electromagnetic radiation that is provided to the photosensitive material.

A method for making at least one structure having sidewalls with different inclinations includes providing a stack including a substrate having a layer of a positive resin whose tone could be reversed when exposed to an insolation dose D<Dinversion, the patterns exposed to the dose Dinversion not being sensitive to creeping at the glass-transition temperature Tfluage of the resin; forming a non-sensitive first pattern by exposing the resin to a first dose D1≥Dinversion, the first pattern having a first sidewall having a first inclination; and forming a creep-sensitive second pattern by exposing the resin to a second dose D2<Dinversion. Creeping is performed by applying a temperature T≥Tfluage to make the second pattern creep over a portion of the first pattern by leaving uncovered at least partially the first sidewall of the first pattern, and defining at least one second sidewall having a second inclination different from the first inclination.

The embodiments of the disclosure provide a patterning method, which includes the following processes. A target layer is formed on a substrate. A hard mask layer is formed over the target layer. A first patterning process is performed on the hard mask layer by using a photomask having a first pattern with a first pitch. The photomask is shifted along a first direction by a first distance. A second patterning process is performed on the hard mask layer by using the photomask that has been shifted, so as to form a patterned hard mask. The target layer is patterned using the patterned hard mask to form a patterned target layer. The target layer has a second pattern with a second pitch less than the first pitch.

An image analysis method for identifying features in an image of a part of an array of features formed by a multi-step process, the method comprising: analyzing variations in features visible in the image; and associating features of the image with steps of the multi-step process based at least in part on results of the analyzing.

A method for manufacturing a semiconductor device, includes receiving a first layout including patterns for the manufacturing of the semiconductor device, generating a second layout by performing machine learning-based process proximity correction (PPC) based on features of the patterns of the first layout, generating a third layout by performing optical proximity correction (OPC) on the second layout, and performing a multiple patterning process based on the third layout. The multiple patterning process includes patterning first-type patterns, and patterning second-type patterns. The machine learning-based process proximity correction is performed based on features of the first-type patterns and features of the second-type patterns.

A pattern decomposition method including following steps is provided. A target pattern is provided, wherein the target pattern includes first patterns and second patterns alternately arranged, and the width of the second pattern is greater than the width of the first pattern. Each of the second patterns is decomposed into a third pattern and a fourth pattern, wherein the third pattern and the fourth pattern have an overlapping portion, and a pattern formed by overlapping the third pattern and the fourth pattern is the same as the second pattern. The third patterns and the first pattern adjacent to the fourth pattern are designated as first photomask patterns of a first photomask. The fourth patterns and the first pattern adjacent to the third pattern are designated as second photomask patterns of a second photomask.