Embodiments of a photolithographic machine with two or more camera systems (i.e., projection lens systems) are described herein. The photolithographic machine may include two or more cameras independently operated and controlled for exposing integrated circuit, flat panel display, and other substrates used in manufacturing semiconductor electronics. The cameras may be independently controlled to move laterally in the x-axis (i.e., not fixed). The independent control can include movement, focusing, tilt, reticle position, among other things.

The present invention provides a large die, a method of forming the large die and a large die wafer. The method includes: providing a wafer containing a plurality of large dies each having a size greater than that of a maximum field of exposure of a stepper, each large die including at least two die portions to be stitched together, the die portions including a substrate and a first metal layer, the first metal layer including at least to-be-interconnected metal layers for interconnection of the die portions; and forming a second metal layer including at least inter-die interconnecting metal layers crossing dummy dicing margins between adjacent die portions and coming into electrical connection with the to-be-interconnected metal layers of the adjacent die portions. The present invention allows interconnection of the die portions to be stitched together in each large die.

A pattern decomposition method including following steps is provided. A target pattern is provided, wherein the target pattern includes first patterns and second patterns alternately arranged, and the width of the second pattern is greater than the width of the first pattern. Each of the second patterns is decomposed into a third pattern and a fourth pattern, wherein the third pattern and the fourth pattern have an overlapping portion, and a pattern formed by overlapping the third pattern and the fourth pattern is the same as the second pattern. The third patterns and the first pattern adjacent to the fourth pattern are designated as first photomask patterns of a first photomask. The fourth patterns and the first pattern adjacent to the third pattern are designated as second photomask patterns of a second photomask.

A mask correction method, a mask correction device for double patterning, and a training method for a layout machine learning model are provided. The mask correction method for double patterning includes the following steps. A target layout is obtained. The target layout is decomposed into two sub-layouts, which overlap at a stitch region. A size of the stitch region is analyzed by the layout machine learning model according to the target layout. The layout machine learning model is established according to a three-dimensional information after etching. An optical proximity correction (OPC) procedure is performed on the sub-layouts.

Examples of a multiple-mask multiple-exposure lithographic technique and suitable masks are provided herein. In some examples, a photomask includes a die area and a stitching region disposed adjacent to the die area and along a boundary of the photomask. The stitching region includes a mask feature for forming an integrated circuit feature and an alignment mark for in-chip overlay measurement.

A mask includes a first region and a second region. The first region includes a first light-shielding strip and a second light-shielding strip, the second region includes a third light-shielding strip, the first light-shielding strip, the second light-shielding strip is located between the first light-shielding strip and the third light-shielding strip, the first light-shielding strip, the second light-shielding strip and the third light-shielding strip are configured to shield light and bound spaces, and the spaces are configured in such a manner that light is allowed to pass through the spaces. A width of the first light-shielding strip in a first direction is larger than a width of the second light-shielding strip in the first direction, and the width of the second light-shielding strip in the first direction is larger than a width of the third light-shielding strip in the first direction.

Aspects of disclosure provide a method for attaching wiring connections to a component using both design and field measured data of the component to produce accurate wiring connections.

A mask is provided that includes a first graphic region and a second graphic region disposed along a first direction. The first graphic region comprises a first splicing exposure region. The second graphic region comprises a second splicing exposure region. The first splicing exposure region is used for, after being translated along a first vector, forming a first splicing auxiliary region, and the first splicing auxiliary region coincides with the second splicing exposure region.

The present application discloses a method for measuring stitching overlay accuracy of image sensor stitching manufacturing, forming an A-type overlay pattern mark and a corresponding B-type overlay pattern mark on the edge of each rectangular pixel area to be stitched; after the A-type overlay pattern mark and the B-type overlay pattern mark are stitched and exposed, performing metrology by means of a scanning electron microscope to obtain dimension features; and according to the dimension features of the A-type overlay pattern mark and the B-type overlay pattern mark stitched together and exposed and measured by the scanning electron microscope, determining stitching overlay accuracy of two adjacent rectangular pixel areas. The present application can achieve direct metrology on the overlay pattern mark on the stitched pixel area of a product, facilitating timely and accurate monitoring on the stitching overlay accuracy of image sensor stitching manufacturing.

Aspects of disclosure provide a method for attaching wiring connections to a component using both design and field measured data of the component to produce accurate wiring connections.