Embodiments of this invention provide a measurement map configuration method and apparatus. A wafer to be inspected is provided. The wafer includes a plurality of inspection marks. A first inspection result is obtained based on a first set of inspection marks. A second set of inspection marks is selected based on a preset rule. The second set of inspection marks is less than the first set of inspection marks. A second inspection result is obtained based on the second set of inspection marks. If an overlay accuracy of the second inspection result matches an overlay accuracy the first inspection result, a measurement map for the wafer is set based on target inspection marks. The target inspection marks are the second set of inspection marks of the measurement map.

Methods and systems for selecting measurement locations on a wafer for subsequent detailed measurements employed to characterize the entire wafer are described herein. High throughput measurements are performed at a relatively large number of measurement sites on a wafer. The measurement signals are transformed to a new mathematical basis and reduced to a significantly smaller dimension in the new basis. A set of representative measurement sites is selected based on analyzing variation of the high throughput measurement signals. In some embodiments, the spectra are subdivided into a set of different groups. The spectra are grouped together to minimize variance within each group. Furthermore, a die location is selected that is representative of the variance exhibited by the die in each group. A spectrum of a measurement site and corresponding wafer location is selected to correspond most closely to the center point of each cluster.

A metrology system may receive design data including a layout of fabricated instances of a structure on a sample. The system may further receive detection signals from the metrology tool associated within a field of view including multiple of the fabricated instances of the structure. The system may further generate design-assisted composite data for the structure by combining detection signals from one or more common features of the structure associated with the fabricated instances of the structure within the field of view using the design data. The system may further generate one or more metrology measurements of the structure based on the design-assisted composite data.

A metrology system can be integrated within a lithographic apparatus to provide integrated metrology within the lithographic process. However, this integration can result in a throughput or productivity impact of the whole lithographic apparatus which can be difficult to predict. It is therefore proposed to acquire throughput information associated with a throughput of a plurality of substrates within a lithographic apparatus, the throughput information including a throughput parameter, and predict, using a throughput simulator, a throughput using the throughput parameter as an input parameter. The throughput simulator may be calibrated using the acquired throughput information. The impact of at least one change of a throughput parameter on the throughput of the lithographic apparatus may be predicted using the throughput simulator.

A method may include, but is not limited to, receiving a measurement including a metrology parameter for a layer of a metrology target and an alignment mark from an overlay metrology tool prior to a lithography process; deriving a merit figure from the metrology parameter and the alignment mark; deriving a correction factor from the merit figure; providing the correction factor to the lithography process via a feed forward process; receiving an additional measurement including an additional metrology parameter for the layer and an additional layer from an additional overlay metrology tool after the lithography process; deriving an adjustment from the additional metrology parameter; and providing the adjustment to the lithography process via a feedback process.

A method for process analysis includes acquiring first inspection data, using a first inspection modality, with respect to a substrate having multiple instances of a predefined pattern of features formed thereon using different, respective sets of process parameters. Characteristics of defects identified in the first inspection data are processed so as to select a first set of defect locations in which the first inspection data are indicative of an influence of the process parameters on the defects. Second inspection data are acquired, using a second inspection modality having a finer resolution than the first inspection modality, of the substrate at the locations in the first set. The defects appearing in the second inspection data are analyzed so as to select, from within the first set of the locations, a second set of the locations in which the second inspection data are indicative of an optimal range of the process parameters.

A semiconductor device metrology including creating a time-domain representation of wavelength-domain measurement data of light reflected by a patterned structure of a semiconductor device, selecting a relevant and irrelevant portion of the time-domain representation, and determining one or more measurements of one or more parameters of interest of the patterned structure by performing model-based processing using the relevant portion of the time-domain representation.

A method for process analysis includes acquiring first inspection data, using a first inspection modality, with respect to a substrate having multiple instances of a predefined pattern of features formed thereon using different, respective sets of process parameters. Characteristics of defects identified in the first inspection data are processed so as to select a first set of defect locations in which the first inspection data are indicative of an influence of the process parameters on the defects. Second inspection data are acquired, using a second inspection modality having a finer resolution than the first inspection modality, of the substrate at the locations in the first set. The defects appearing in the second inspection data are analyzed so as to select, from within the first set of the locations, a second set of the locations in which the second inspection data are indicative of an optimal range of the process parameters.

Embodiments of the present disclosure provide systems and methods for enhancing the semiconductor manufacturing yield. Embodiments of the present disclosure provide a yield improvement system. The system comprises a training tool configured to generate training data based on receipt of one or more verified results of an inspection of a first substrate. The system also comprises a point determination tool configured to determine one or more regions on a second substrate to inspect based on the training data, weak point information for the second substrate, and an exposure recipe for a scanner of the second substrate.

A method for process analysis includes acquiring first inspection data, using a first inspection modality, with respect to a substrate having multiple instances of a predefined pattern of features formed thereon using different, respective sets of process parameters. Characteristics of defects identified in the first inspection data are processed so as to select a first set of defect locations in which the first inspection data are indicative of an influence of the process parameters on the defects. Second inspection data are acquired, using a second inspection modality having a finer resolution than the first inspection modality, of the substrate at the locations in the first set. The defects appearing in the second inspection data are analyzed so as to select, from within the first set of the locations, a second set of the locations in which the second inspection data are indicative of an optimal range of the process parameters.