Substrate tables for lithography and methods of handling a substrate. In one arrangement, a substrate table includes one or more membranes. An actuation system deforms each membrane to change a height of a portion of the membrane. In another arrangement, a substrate table includes one or more membranes and a clamping system for clamping a substrate to the substrate table, wherein the clamping deforms each membrane by pressing the substrate against the membrane.

A semiconductor structure and a method for managing semiconductor wafer stress are disclosed. The semiconductor structure includes a semiconductor wafer, a first stress layer disposed on and in contact with a backside of the semiconductor wafer, and a second stress layer on and in contact with the first stress layer. The first stress layer exerts a first stress on the semiconductor wafer and the second layer exerts a second stress on the semiconductor wafer that is opposite the first backside stress. The method includes forming a first stress layer on and in contact with a backside of a semiconductor wafer, and further forming a second stress layer on and in contact with the first stress layer. The first stress layer exerts a first stress on the semiconductor wafer and the second stress layer exerts a second stress on the semiconductor wafer that is opposite to the first stress.

In an embodiment, an apparatus includes an energy source, a support platform for holding a wafer, an optical path extending from the energy source to the support platform, and a photomask aligned such that a patterned major surface of the photomask is parallel to the force of gravity, where the optical path passes through the photomask, where the patterned major surface of the photomask is perpendicular to a topmost surface of the support platform.

A lithography apparatus is provided. The lithography apparatus includes a wafer stage configured to secure a semiconductor wafer and having a plurality of electrodes. The lithography apparatus also includes an exposure tool configured to perform an exposure process by projecting an extreme ultraviolet (EUV) light on the semiconductor wafer. The lithography apparatus further includes a controller configured to control power supplied to the electrodes to have a first adjusted voltage during the exposure process for a first group of exposure fields on the semiconductor wafer so as to secure the semiconductor wafer to the wafer stage. The first adjusted voltage is in a range from about 1.6 kV to about 3.2 kV.

Methods and systems are described for reducing adhesion and controlling friction between a wafer and a wafer table during semiconductor photolithography wherein the tops of burls on the wafer table have a layer with a nanoscale topography.

A carrier system and method carries an object to an object mounting member provided with an object mounting section. The system includes: a measurement device which obtains information related to a flatness of the object; a carrier member that carries the object; and a controller which controls a driving speed of the carrier member using the information related to the flatness of the object obtained by the measurement device.

A mask for use in a semiconductor lithography process includes a substrate, a mask pattern disposed on the substrate, and a light absorbing border surrounding the mask pattern. The light absorbing border is inset from at least two edges of the substrate to define a peripheral region outside of the light absorbing border. In some designs, a first peripheral region extends from an outer perimeter of the light absorbing border to a first edge of the substrate, and a second peripheral region that extends from the outer perimeter of the light absorbing border to a second edge of the substrate, where the first edge of the substrate and the second edge of the substrate are on opposite sides of the mask pattern.

A method for preparing a substrate for an exposure process of a lithographic manufacturing method, the method including imposing different local temperatures across the substrate so as to induce different thermal expansion across the substrate before the exposure process. This method is for compensating for deformation of the substrate induced when the substrate is positioned on a substrate table of a lithographic apparatus. There is also provided a local temperature applicator to implement this technique and to a lithographic apparatus including such a local temperature applicator.

A method for monitoring flatness of a wafer table includes: acquiring a yield and original focus data of a wafer in real time; obtaining an edge flatness curve of a wafer table based on the original focus data; obtaining a yield curve of the wafer based on the yield of the wafer; obtaining a trend diagram of the edge flatness and the yield over time based on the edge flatness curve and the yield curve; and determining, based on the trend diagram, an edge flatness value of the wafer table when the wafer table is replaced.

Provided are methods of reducing the stress of a semiconductor wafer. A wafer map of a free-standing wafer is created using metrology tools. The wafer map is then converted into a power spectral density (PSD) using a spatial frequency scale. The fundamental component of bow is then compensated with a uniform film, e.g., silicon nitride (SiN), deposited on the back side of the wafer.