Integrated circuit devices might include a voltage regulator comprising an input and an output, a selectively activated current path connected between the input and output, and a controller configured to cause the integrated circuit device to connect the output to the input through the current path when a voltage level of the input has a first voltage level, maintain the connection of the output and the input through the current path until the voltage level of the input has a second voltage level higher than the first voltage level, isolate the output from the input through the current path after the voltage level of the input has the second voltage level, and regulate a voltage level of the output while the output is isolated from the input through the current path.

Integrated circuit devices might include a voltage regulator comprising an input and an output, a selectively activated current path connected between the input and output, and a controller configured to cause the integrated circuit device to connect the output to the input through the current path when a voltage level of the input has a first voltage level, maintain the connection of the output and the input through the current path until the voltage level of the input has a second voltage level higher than the first voltage level, isolate the output from the input through the current path after the voltage level of the input has the second voltage level, and regulate a voltage level of the output while the output is isolated from the input through the current path.

A comparison control circuit is adapted to analog-to-digital converters and low-dropout regulators. The comparison control circuit includes a comparator, a Schmitt trigger, a capacitor set and a logic circuit. The comparator is configured to output a comparison signal according to a first input signal and a second input signal, wherein the comparison signal is a first high voltage potential or a first low voltage potential. The Schmitt trigger is configured to output a trigger signal according to the comparison signal and a voltage potential range, wherein the voltage potential range is in a range from the first low voltage potential to the first high voltage potential. The capacitor set is configured to adjust the second input signal when being controlled. The logic circuit is configured to control the capacitor set according to the trigger signal to correspondingly adjust the second input signal.

A comparison control circuit is adapted to analog-to-digital converters and low-dropout regulators. The comparison control circuit includes a comparator, a Schmitt trigger, a capacitor set and a logic circuit. The comparator is configured to output a comparison signal according to a first input signal and a second input signal, wherein the comparison signal is a first high voltage potential or a first low voltage potential. The Schmitt trigger is configured to output a trigger signal according to the comparison signal and a voltage potential range, wherein the voltage potential range is in a range from the first low voltage potential to the first high voltage potential. The capacitor set is configured to adjust the second input signal when being controlled. The logic circuit is configured to control the capacitor set according to the trigger signal to correspondingly adjust the second input signal.

A power management circuit for fast average power tracking (APT) voltage switching is provided. The power management circuit includes a primary voltage circuit configured to generate an APT voltage based on an APT target voltage. However, the primary voltage circuit may be inherently slow in ramping up the APT voltage to the APT target voltage. As such, a secondary voltage circuit is provided in the power management circuit to help drive the APT voltage to a desired level by a defined temporal limit. Once the APT voltage reaches the desired level, the secondary voltage circuit will automatically shut off, while the primary voltage circuit continues operating at a selected duty cycle to maintain the APT voltage at the APT target voltage. By utilizing the secondary voltage circuit to quickly drive up the APT voltage, the power management circuit is capable of supporting dynamic power control under stringent switching delay budget.

A power management circuit for fast average power tracking (APT) voltage switching is provided. The power management circuit includes a primary voltage circuit configured to generate an APT voltage based on an APT target voltage. However, the primary voltage circuit may be inherently slow in ramping up the APT voltage to the APT target voltage. As such, a secondary voltage circuit is provided in the power management circuit to help drive the APT voltage to a desired level by a defined temporal limit. Once the APT voltage reaches the desired level, the secondary voltage circuit will automatically shut off, while the primary voltage circuit continues operating at a selected duty cycle to maintain the APT voltage at the APT target voltage. By utilizing the secondary voltage circuit to quickly drive up the APT voltage, the power management circuit is capable of supporting dynamic power control under stringent switching delay budget.

Digital logic voltage regulators and related methods generate a regulated voltage via controlled switching of a power transistor. A digital logic voltage regulator includes a voltage level comparator, a power transistor, and a charge accumulator. The voltage level comparator generates a digital control signal that alternates between a first voltage level and a second voltage level in response to changes in relative voltage level between the regulated output voltage and the target voltage. The digital control signal causes the power transistor to switch from off to on in response to a reduction of the regulated output voltage relative to the target voltage and causes the power transistor to switch from on to off in response to an increase of the regulated output voltage relative to the target voltage. The charge accumulator decreases variation in the regulated output voltage that would occur without the charge accumulator.

Digital logic voltage regulators and related methods generate a regulated voltage via controlled switching of a power transistor. A digital logic voltage regulator includes a voltage level comparator, a power transistor, and a charge accumulator. The voltage level comparator generates a digital control signal that alternates between a first voltage level and a second voltage level in response to changes in relative voltage level between the regulated output voltage and the target voltage. The digital control signal causes the power transistor to switch from off to on in response to a reduction of the regulated output voltage relative to the target voltage and causes the power transistor to switch from on to off in response to an increase of the regulated output voltage relative to the target voltage. The charge accumulator decreases variation in the regulated output voltage that would occur without the charge accumulator.

Disclosed is a low dropout regulator which includes a first resistor, a first transistor including a gate terminal connected with a first end of the first resistor, a source terminal connected with a power supply voltage terminal, and a drain terminal connected with a first node, an operational amplifier including input terminals respectively connected with a reference voltage and the first node and an output terminal, a second transistor including a gate terminal connected with the output terminal of the operational amplifier, a source terminal connected with the first node, and a drain terminal connected with a second node, a third transistor including a gate terminal connected with a second end of the first resistor, a source terminal connected with the power supply voltage terminal, and a drain terminal connected with a third node, and a current source connected between the second node and a ground voltage terminal.

Disclosed is a low dropout regulator which includes a first resistor, a first transistor including a gate terminal connected with a first end of the first resistor, a source terminal connected with a power supply voltage terminal, and a drain terminal connected with a first node, an operational amplifier including input terminals respectively connected with a reference voltage and the first node and an output terminal, a second transistor including a gate terminal connected with the output terminal of the operational amplifier, a source terminal connected with the first node, and a drain terminal connected with a second node, a third transistor including a gate terminal connected with a second end of the first resistor, a source terminal connected with the power supply voltage terminal, and a drain terminal connected with a third node, and a current source connected between the second node and a ground voltage terminal.