A method comprises a Dynamic Equality of Service (DEoS) arbiter of a switch computing port DEoS metrics based on dynamic input activity of source nodes into input ports of the switch. Based on the port DEoS metrics, the arbiter selects an input port of the switch to make a through-connection to an output port of the switch. The port DEoS metrics can be based on node DEoS metrics including DEoS counters, and/or quantization ranges of DEoS counters, associated with the source nodes. A switching apparatus comprises a switch, a plurality of nodes coupled to the switch, and a DEoS arbiter. The switching apparatus can further comprise a first and second DEoS counter. The DEoS arbiter can perform operations of the method to arbitrate among input ports of the switch to make a through-connection.

A device configured to receive a set of bits for a first package from a previous device of a plurality of devices connected in a daisy chain configuration, the set of bits for the first package including a first priority value and if the device does not have a second package for output to a destination device of the plurality of devices, output the set of bits for the first package to a subsequent device of the plurality of devices. When the device has the second package for output to the destination device of the plurality of devices, the device is configured to determine whether the second priority value is higher than the first priority value and if the second priority value is higher than the first priority value output a set of bits for the second package to the subsequent device of the plurality of devices.

Methods, systems, and devices for providing computer implemented services using managed systems are disclosed. To provide the computer implemented services, the managed systems may need to operate in a predetermined manner conducive to, for example, execution of applications that provide the computer implemented services. Similarly, the managed system may need access to certain hardware resources (e.g., and also software resources such as drivers, firmware, etc.) to provide the desired computer implemented services. To improve the likelihood of the computer implemented services being provided, the managed devices may be managed using a subscription based model. The subscription model may utilize a highly accessible service to obtain information regarding desired capabilities (e.g., a subscription) of a managed system, and use the acquired information to automatically configure and manage the features and capabilities of the managed systems.

According to one embodiment, a path obfuscation system includes first and second hardware devices, and first and second interfaces configured to provide communication between the first and second hardware devices using a security protocol and data model (SPDM) protocol. The first hardware device comprises computer-executable instructions to receive a message to be transmitted to the second hardware device, segment the message into multiple groups of packets, and randomly select either the first or second interface to transmit each group of packet to the second hardware device.

Circuits and methods enabling common control of an agent device by two or more buses, particularly MIPI RFFE serial buses. In essence, the invention provides flagging signals designating completed register write operations to denote which of two registers are active, such that synchronization is accomplished in a clock-free manner. One embodiment includes at least two decoders, each including a common register and a bus (S/P) decoder coupled to a respective bus and to the common register. The S/P decoder asserts a write-complete signal when a write operation to a corresponding common register is completed. A multiplexer has at least two selectable input bus ports coupled to the common registers within the at least two decoders. A selection circuit selects an input bus port of the multiplexer in response to the assertion of a last write-complete signal from the S/P decoders.

Bus system comprising a first bus and a second bus, wherein the first bus is connected to the second bus through a bridge and a multiplexer. A first master has access to the second bus via the first bus, the bridge and the multiplexer. A second master has access to the second bus via the multiplexer. The bridge comprises an arbitration unit which is arranged to allow both a first master and a second master access to the second bus in such a way that no access is disturbed or lost.

Channel availability information associated with data traffic between a Master and a Slave within an interconnection network (“ICN”) in a System-on-Chip (“SoC”) is monitored by a channel performance monitor in order to improve the performance of the ICN. The channel availability information is fed back to certain Masters to control their data traffic into the ICN. The channel performance monitor monitors and evaluates the data traffic handled by switches within the ICN that can potentially interfere with communication paths between particular Masters and Slaves, and control the initiation of data traffic from predetermined Masters.

An apparatus comprises an interconnect providing communication paths between agents coupled to the interconnect. A coordination agent is provided which performs an operation requiring sending a request to each of a plurality of target agents, and receiving a response from each of the target agents, the operation being unable to complete until the response has been received from each of the target agents. Storage circuitry is provided which is accessible to the coordination agent and configured to store, for each agent that the coordination agent may communicate with via the interconnect, a latency indication for communication between that agent and the coordination agent. The coordination agent is configured, prior to performing the operation, to determine a sending order in which to send the request to each of the target agents, the sending order being determined in dependence on the latency indication for each of the target agents.

In an embodiment, a system on a chip (SOC) comprises a semiconductor die on which circuitry is formed, wherein the circuitry comprises a memory controller circuit and a plurality of networks formed from a plurality of individual network component circuits. The memory controller includes a PIO message control circuit that is configured to receive PIO messages addressed to individual network component circuits and determine whether to send the PIO messages to the individual network component circuits based on determine whether previous PIO messages are pending for the individual network component circuits. The PIO message control circuit is configured to delay a first PIO message at the PIO message control circuit in response to determining that previous PIO message is pending for the addressee of the first PIO message.

In an embodiment, a system on a chip (SOC) comprises a semiconductor die on which circuitry is formed, wherein the circuitry comprises a memory controller circuit and a plurality of networks formed from a plurality of individual network component circuits. The memory controller includes a PIO message control circuit that is configured to receive PIO messages addressed to individual network component circuits and determine whether to send the PIO messages to the individual network component circuits based on determine whether previous PIO messages are pending for the individual network component circuits. The PIO message control circuit is configured to delay a first PIO message at the PIO message control circuit in response to determining that previous PIO message is pending for the addressee of the first PIO message.