An adaptation method between PCIE and SPI realized based on FPGA, comprising following steps: S01: a PCIE equipment sends PCIE information to a mapping module through a PCIE module; S02: the mapping module extracts SPI information from the PCIE information and transmits the SPI information to a SPI equipment through an SPI module; all of the PCIE module, the mapping module and the SPI module are located on a FPGA chip; S03: the SPI equipment performs a read/write operation according to the SPI information, and feeds back SPI operation information subjected to the read/write operation to the mapping module; S04: the mapping module modifies PCIE information according to the SPI operation information to obtain PCIE feedback information; S05: the PCIE equipment reads the PCIE feedback information through the PCIE module. The present invention provides a conversion adapter and a method between PCIE and SPI realized based on FPGA to realize conversion for a PCI interface and a SPI interface, so as to perform a read/write operation of an AD chip with the SPI interface or a DA chip with the SPI interface, which has universal applicability.

Various data bus monitoring, analysis, and logging systems, devices, and methods are described herein. In one example, an apparatus includes a first circuit configured to monitor first packets among traffic carried by one or more first directional lanes of a communication link established between a host and one or more endpoint devices and determine header information for the first packets. The apparatus includes a second circuit configured to detect second packets among traffic carried by one or more second directional lanes of the communication link based at least in part on the header information determined for the first packets. The apparatus includes an analysis element configured to establish transaction metadata comprising properties of transactions on the communication link based at least on correlations among the first packets and the second packets.

A method, system and computer program product are provided for implementing coherent accelerator function isolation for virtualization in an input/output (IO) adapter in a computer system. A coherent accelerator provides accelerator function units (AFUs), each AFU is adapted to operate independently of the other AFUs to perform a computing task that can be implemented within application software on a processor. The AFU has access to system memory bound to the application software and is adapted to make copies of that memory within AFU memory-cache in the AFU. As part of this memory coherency domain, each of the AFU memory-cache and processor memory-cache is adapted to be aware of changes to data commonly in either cache as well as data changed in memory of which the respective cache contains a copy.

Aspects include obtaining data to be transformed. A selected transformation to be applied to the data is determined based on a storage block address list entry (SBALE) in a storage block address list (SBAL). The SBALE includes at least one field that is used in determining the selected transformation to be applied. The selected transformation is applied on the data to generate transformed data and the transformed data is placed in a location specified by the SBAL.

A method can include receiving network packets including forwarding plane packets; evaluating header information of the network packets to map network packets to any of a plurality of destinations on the module, each destination corresponding to any of a plurality of services executed by offload processors of the module; configuring operations of the offload processors; and in response to forwarding plane packets, executing operations on the forwarding plane packets; wherein the receiving, evaluation and processing of the forwarding plane packets are performed independent of the host processor. Corresponding systems and methods are also disclosed.

Provided are a method and apparatus for multi-bus device fused access. The method includes: receiving, by a bus, an instruction for accessing a fused node of a device, which instruction containing a matching word, an initial address, and an offset; performing matching according to the matching word and activating a fused drive; acquiring, by the fused drive, the initial address and the offset from the instruction on the bus respectively; computing an address of a first bus of the device according to the initial address, and computing an address of a second bus of the device according to the initial address and the offset; and accessing the device according to the address of the first bus so as to acquire first information, and accessing the device according to the address of the second bus so as to acquire second information.

A configurable multi-function Peripheral Component Interchange Express (PCIe) endpoint controller, integrated in a system-on-chip (SoC), that exposes multiple functions of multiple processing subsystems (e.g., peripherals) to a host. The SoC may include a centralized transaction tunneling unit and a multi-function interrupt manager. The processing subsystems output data to the host via the centralized transaction tunneling unit, which translates addresses provided by the host to a local address of the SoC. Therefore, the centralized transaction tunneling unit enables those processing subsystems to consume addresses provided by the host without the need for software intervention and software-based translation. The SoC may also provide isolation between each function provided by the processing systems. The multi-function interrupt manager enables the endpoint controller to propagate interrupt messages received from the processing subsystems to the host.

A data transmission system and an operation method thereof are provided. The data transmission system includes a host, a first device and a second device. The host is configured to set a voltage base of a transmission signal, and configured to pull down or up the transmission signal based on the voltage base of the transmission signal to form a plurality of glitches. The first device is connected to the host to receive the transmission signal. The first device obtains a digital content of the transmission signal according to the glitches, if the voltage base of the transmission signal is set as a first base. The second device is connected to the host to receive the transmission signal. The second device obtains the digital content of the transmission signal according to the glitches, if the voltage base of the transmission signal is set as a second base.

In one embodiment, an apparatus includes a processor comprising an address translation cache (ATC); a shared work queue (SWQ) associated with the ATC, and a port to couple to a host processor over a Peripheral Component Interconnect Express (PCIe)-based link. The apparatus also includes circuitry to receive address translation information from a memory management unit of the host processor that includes virtual memory address to physical memory address translations, store the address translation information in the ATC, receive an invalidation command from the host processor indicating an invalidation of address translation information stored in the ATC, modify the address translation information in the ATC based on the invalidation command, and store completion data in a memory location indicated by the invalidation command.

A peripheral proxy subsystem is placed between multiple hosts, each having a root controller, and single root I/O virtualization (SR-IOV) peripheral devices that are to be shared. The peripheral proxy subsystem provides a root controller for coupling to the endpoint of the SR-IOV peripheral device or devices and multiple endpoints for coupling to the root controllers of the hosts. The peripheral proxy subsystem maps the virtual functions of an SR-IOV peripheral device to the multiple endpoints as desired to allow the virtual functions to be allocated to the hosts. The physical function of the SR-IOV peripheral device is managed by the peripheral proxy device to provide the desired number of virtual functions. The virtual functions of the SR-IOV peripheral device are then presented to the appropriate host as a physical function or a virtual function.