[Object] Effectively perform data communication [Solving Means] A communication device includes: a LINK that generates a first output signal on a basis of a first external signal from a first external device, outputs the first output signal to a second external device, generates a second output signal on a basis of a second external signal from the second external device, and outputs the second output signal to the first external device, in which each of the first output signal and the second external signal includes command information indicating content of a command transmitted from the first external device, final-destination-device-identification-information for identifying a final destination device of data transmitted from the first external device, internal address information indicating an internal address of the final destination device, data length information indicating a length of the data transmitted from the first external device, and data-end-position-information indicating an end position of the data transmitted from the first external device.

In some embodiments, a system is provided for communicating USB information via an extension medium. The system comprises an upstream facing port device (UFP device) and a downstream facing port device (DFP device). The UFP device and the DFP device are communicatively coupled via a non-USB extension medium, and allow a host device communicatively coupled to the UFP device and a USB device communicatively coupled to the DFP device to communicate via USB-compliant techniques. In some embodiments, the DFP device generates synthetic request packets to request additional data packets from the USB device compared to those requested by the host device. In some embodiments, the DFP device is configured to store a request packet in a packet queue if the request packet is received from the UFP device while the DFP device is busy receiving a response to a previous synthetic request packet from the USB device.

A data transmission method according to an I2C protocol and a transmission apparatus includes: a first transmission chip obtains I2C data from a first device, wherein the I2C data is data sent by the first device to a second device. The first transmission chip sends first feedback information to the first device, wherein the first feedback information is used to indicate whether the I2C data is successfully received. The first transmission chip forwards the I2C data to a second transmission chip corresponding to the second device. The first transmission chip receives second feedback information from the second transmission chip, and the second feedback information is used to indicate whether the I2C data is successfully received. The first transmission chip stores the second feedback information in a first storage space that is storage space of the first transmission chip.

[Object] Effectively perform data communication [Solving Means] A communication device includes: a LINK that generates a first output signal on a basis of a first external signal from a first external device, outputs the first output signal to a second external device, generates a second output signal on a basis of a second external signal from the second external device, and outputs the second output signal to the first external device, in which each of the first output signal and the second external signal includes command information indicating content of a command transmitted from the first external device, final-destination-device-identification-information for identifying a final destination device of data transmitted from the first external device, internal address information indicating an internal address of the final destination device, data length information indicating a length of the data transmitted from the first external device, and data-end-position-information indicating an end position of the data transmitted from the first external device.

A storage system controller chip includes routing circuitry comprising a host interface for coupling to a host device and an extension interface for coupling to a secondary controller chip. A host controller is coupled to a logical interface of the routing circuitry for receiving a host data access command from the host device via the host interface and logical interface. The routing circuitry transfers the host data access command to the secondary controller chip via the extension interface. The storage system controller chip further includes processor circuitry coupled to the logical interface of the routing circuitry. The processor circuitry receives an indication from the secondary controller chip via the extension interface that execution of the host data access command has been completed by the secondary controller chip and instructs the host controller to notify the host device that execution of the host data access command has been completed.

In one embodiment, an apparatus includes a host controller to couple to an interconnect to which a plurality of devices may be coupled. The host controller may include: a first driver to drive first information onto a first line of the interconnect; a second driver to drive a clock signal onto a second line of the interconnect; and a mode control circuit to cause the second driver to drive the clock signal onto the second line of the interconnect in a first mode and to cause the first driver and the second driver to drive differential information onto the first line and the second line of the interconnect in a second mode. Other embodiments are described and claimed.

An inter integrated circuit (I.sup.2C)-based communication method incudes when an I.sup.2C signal is encapsulated into a data packet for transparent transmission, an I.sup.2C status is indicated by a first field in a packet header of the data packet. The data packet may have no load part, or the data packet has a load part but the load part is used to carry a slave address, a read/write flag, or I.sup.2C data. Because the I.sup.2C status is indicated in the packet header of the data packet, the I.sup.2C status may be encapsulated in a same data packet together with the slave address, the read/write flag, or the I.sup.2C data. In other words, the I.sup.2C status may not need to occupy one data packet separately.

An interface bridge to enable communication between a first integrated circuit die and a second integrated circuit die is disclosed. The two integrated circuit die may be connected via chip-to-chip interconnects. The first integrated circuit die may include programmable logic fabric. The second integrated circuit die may support the first integrated circuit die. The first integrated circuit die and the secondary integrated circuit die may communicate with one another via the chip-to-chip interconnects using an interface bridge. The first and second component integrated circuits may include circuitry to implement the interface bridge, which may provide source-synchronous communication using a data receive clock from the second integrated circuit die to the first integrated circuit die.

A system for data transmission between two devices, including an output device having a binary output interface and a first field device having a binary input interface connected in a signal-transmitting manner to the binary output interface via a unidirectional connection. The output device includes a signal processing module which is set up to convert a data set to be transmitted to a binary, discrete-time signal in accordance with a serial protocol. The first field device includes a signal processing module which is set up to convert the received binary, discrete-time signal to the data set in accordance with the serial protocol. The invention further relates to a valve system.

Examples disclosed herein include are computing device hardware components, computing devices, systems, machine-readable mediums, and interconnect protocols that provide for code object measurement of a peripheral device and a method for accessing the measurements to verify integrity across a computing interconnect (e.g., Peripheral Component Interconnect Express—PCIe). For example, a cryptographic processor of a PCIe endpoint (such as a peripheral) may take a measurement (e.g., computing a hash value) of a code object on the device prior to executing the code object. This measurement may be placed in a register that is accessible to another component, such as a host operating system across a PCIe bus for interrogation. The host operating system may utilize an interconnect protocol, such as a PCIe protocol to access the measurement. These measurements may be consumed by a Trusted Platform Manager or other components of a host system that may verify the measurements.