A system and apparatus can include a port for transmitting data; and a link coupled to the port. The port can include a physical layer device (PHY) to decode a physical layer packet, the physical layer packet received across the link. The physical layer packet can include a first bit sequence corresponding to a first ordered set, and a second bit sequence corresponding to a second ordered set, the first bit sequence immediately adjacent to the second bit sequence. The first ordered set is received at a predetermined ordered set interval, which can occur following a flow control unit (flit). The first ordered set comprises eight bytes and the second ordered set comprises eight bytes. In embodiments, bit errors in the ordered sets can be determined by checking bits received against expected bits for the ordered set interval.

In aspects, a Local Interconnect Network (LIN) communication circuit including a first LIN master associated with a first LIN bus and a second LIN master associated with a second LIN bus is disclosed. A data link is connected between the first and second LIN masters. A first mirroring client is established at the first LIN master for receiving message bits corresponding to a LIN message in a first slot on the first LIN bus and for transmitting the message bits bitwise over the data link. A second mirroring client is established at the second LIN master for receiving the message bits and transmitting them over the second LIN bus. The first and second LIN masters include synchronised schedule tables such that the message bits on the second LIN bus are transmitted in a corresponding slot to the first.

According to one embodiment, a path obfuscation system includes first and second hardware devices, and first and second interfaces configured to provide communication between the first and second hardware devices using a security protocol and data model (SPDM) protocol. The first hardware device comprises computer-executable instructions to receive a message to be transmitted to the second hardware device, segment the message into multiple groups of packets, and randomly select either the first or second interface to transmit each group of packet to the second hardware device.

Isochronous channels may be used for transporting non-isochronous data between components in an electronic device, such as when non-isochronous data is aggregated from multiple non-isochronous data streams to achieve a high peak-to-average bandwidth. The aggregated non-isochronous data sources may include data streams from general-purpose communications interfaces for interconnecting components or sub-systems of components within an electronic device. For example, I2C networks for control and programming of components may be connected to other I2C networks through an isochronous channel, such as a differential pair of Soundwire SWI3S wires.

An input/output unit for data acquisition in a field bus system includes a microcontroller that has at least one integrated synchronous serial bus interface and a control device for direct memory access. A signal source for a digital signal is connectable to a digital data input master input, slave output (MISO) of the at least one synchronous serial bus interface. The first synchronous serial interface reads in the digital signal present at the data input MISO at a first clock rate that corresponds to a data transmission rate of the at least one synchronous serial bus interface. The control device for direct memory access forwards the read-in data words to a buffer memory, and periodically fetches the read-in data words from the buffer memory and forwards the read-in data words to a second synchronous serial bus interface or to another bus interface.

Memory systems with a communications bus (and associated systems, devices, and methods) are disclosed herein. In one embodiment, a memory device includes an input/output terminal separate from data terminals of the memory device. The input/output terminal can be operably connected to a memory controller via a communications bus. The memory device can be configured to initiate a communication with the memory controller by outputting a signal via the input/output terminal and/or over the communications bus. The memory device can be configured to output the signal in accordance with a clock signal that is different from a second clock signal user to output or receive data signals via the data terminals. In some embodiments, the memory device is configured to initiate communications over the communication bus only when it possesses a communication token. The communication token can be transferred between memory devices operably connected to the communications bus.

The disclosed computer-implemented method may include (1) receiving, by a first internal physical processor of an accelerator from an external processor, a request to access a result of executing a sensitive application within a secure execution zone of the accelerator having (a) a second internal physical processor and (b) physical memory accessible to the second internal physical processor but inaccessible to the first internal physical processor and the external processor, (2) executing, by the second internal physical processor within the secure execution zone, the sensitive application from the physical memory to generate the result, (3) making, by the second internal physical processor, the result accessible outside of the secure execution zone, and (4) relaying, by the first internal physical processor, the result to the external processor. Various other methods, systems, and computer-readable media are also disclosed.

System and methods for an Advance Centralized Chronos Network on Chip (ACC-NoC) design are disclosed. The ACC-NoC is able to efficiently satisfy interconnect traffic requirements of modern Systems of Chip and simplify top level timing closure while providing high throughput and low latency. The ACC-NoC in a System on Chip may include a centralized intelligent switch and arbitration engine communicatively coupled to different intellectual property (IP) blocks through series of one or more Chronos Channels which transmit data using delay insensitive (DI) codes and quasi-delay-insensitive (QDI) logic.

A method for synchronous serial communication includes encoding, by a master device, a header field to be initially transmitted in a frame with a header identification code and a slave count value that defines a number of slave devices communicatively coupled to the master device. A plurality of address fields to be transmitted in the frame are also encoded by the master device. Each of the address fields corresponding to a different one the slave devices. A first of the address fields to be transmitted in the frame corresponds to a last of the slave devices to receive the header field, and a last of the address fields to be transmitted in the frame corresponds to a first of the slave devices to receive the header field. The frame is transmitted to the slave devices by the master device.

A computer-implemented method includes using a transmitter to send data from the transmitter through a plurality of lanes to a receiver using a synchronous operation mode that includes sending the data from the transmitter through the plurality of lanes to the receiver in a synchronous transmission manner that relies on an alignment between a transmitter clock frequency and a receiver clock frequency. A synchronous operation performance analysis (SOPA) is performed during the synchronous operation mode. A switch from the synchronous operation mode to an asynchronous operation mode is made based on a result of performing the SOPA. The asynchronous operation mode includes sending the data from the transmitter through the plurality of lanes to the receiver without requiring alignment between the transmitter clock frequency and the receiver clock frequency.