A light emitting device includes pixel circuits arranged to form rows and columns and each including a light emitting element, signal lines each extending in a column direction and configured to supply a pixel signal to the pixel circuits, row selection lines each extending in a row direction and configured to supply a row selection signal to the pixel circuits, and column selection lines each extending in the column direction and configured to supply a column selection signal to the pixel circuits. At least one of the pixel circuits includes a light emission control circuit configured to allow the light emitting element of a pixel circuit indicated by the row selection signal and the column selection signal to emit light in a brightness according to the pixel signal that is being supplied to the pixel circuit.

A display device includes a silicon wafer including digital circuits, a micro-light emitting diode (micro-LED) wafer including an array of micro-LEDs, and an indium-gallium-zinc-oxide (IGZO) layer between the silicon wafer and the micro-LED wafer and including analog circuits. The digital circuits are characterized by a first operating supply voltage and are configured to generate digital control signals based on digital display data of an image frame. The analog circuits are characterized by a second operating supply voltage higher than the first operating supply voltage. The analog circuits includes analog storage devices configured to storing analog signals, and transistors controlled by the digital control signals and the analog signals to generate drive currents for driving the array of micro-LEDs. The digital circuits on the silicon wafer or the analog circuits in the IGZO layer include level-shifting circuits at interfaces between the digital circuits and the analog circuits.

Methods and apparatuses relating to controlling an emission of a display panel. In one embodiment, a display driver hardware circuit includes row selection logic to select a number of rows in an emission group of a display panel, wherein the number of rows is adjustable from a single row to a full panel of the display panel, column selection logic to select a number of columns in the emission group of the display panel, wherein the number of columns is adjustable from a single column to the full panel of the display panel, and emission logic to select a number of pulses per data frame to be displayed, wherein the number of pulses per data frame is adjustable from one to a plurality and a pulse length is adjustable from a continuous duty cycle to a non-continuous duty cycle.

Display panel redundancy schemes and methods of operation are described. In an embodiment, and display panel includes an array of drivers (e.g. microdrivers), each of which including multiple portions to independently receive control and pixel bits. In an embodiment, each driver portion is to control a group of redundant emission elements.

An LED driving apparatus for driving an LED array including a plurality of digital-to-analog converters and a plurality of data latch circuits is provided. Each of the digital-to-analog converters is coupled to a corresponding LED, and outputs a driving current according to n-bits pixel data to drive the corresponding LED. Each of the plurality of data latch circuits stores the n-bits pixel data, and is coupled to a corresponding digital-to-analog converter to control the n-bits pixel data to be written into the corresponding digital-to-analog converter. Each of digital-to-analog converters includes n sub-driving current generating circuits. Each of the n sub-driving current generating circuits generates a sub-driving current having a current value corresponding to a bit order of a bit of the n-bits pixel data. The driving current is generated by summing up n sub-driving currents.

A system for generating a voltage at a pixel array includes a plurality of display pixels forming the pixel array, each display pixel comprising a pixel circuit for driving the pixel. The system further comprises a row formatter configured to store a plurality of bits representing image data for a row of display pixels of the LCOS array; a row controller configured to write a subset of the plurality of bits representing image data for a pixel of the row into a plurality of data latches of said pixel circuit; and a waveform generator for generating reference pulses represented by a set of reference bits. The pixel circuit is configured to compare each reference bit to corresponding bits stored in the latches of each pixel circuit, and generate voltage at an electrode of each pixel based on this comparison.

The present embodiments disclose a display device. A display device according to an embodiment of the present disclosure comprises a pixel unit including a plurality of pixels, each including a luminous element and a pixel circuit connected to the luminous element, a clock generator configured to generate a plurality of clock signals each corresponding to each of a plurality of subframes constituting a frame, and a parallel to serial converter configured to convert the plurality of clock signals to a serial clock signal and transfer the serial clock signal to the pixel unit, and wherein the pixel circuit of each pixel includes a first pixel circuit configured to control light-emission and non-emission of the luminous element in response to a control signal applied to each of the plurality of subframes and a second pixel circuit configured to store bit values of image data in the frame and generate the control signal based on the stored bit values and the serial clock signal such that each subframe included in the frame is controlled according to each bit value.

A power management integrated circuit includes a flip-flop circuit configured to perform a logic operation on a start clock signal which sets a driving start time point of a gate driving circuit and an on-clock signal which sets an output start time point of the gate driving circuit; a first AND gate circuit configured to receive one among output signals of the flip-flop circuit and the start clock signal, to perform an AND logic operation thereon, and to generate a gate start signal; and a second AND gate circuit configured to receive the other of the output signals of the flip-flop circuit and the start clock signal, to perform an AND logic operation thereon, and to generate a gate reset signal.

Display panel redundancy schemes and methods of operation are described. In an embodiment, and display panel includes an array of drivers (e.g. microdrivers), each of which including multiple portions to independently receive control and pixel bits. In an embodiment, each driver portion is to control a group of redundant emission elements.

A display is created using “smart pixels.” A smart pixel is a pixel of a display that integrates the pixel pipeline as part of the pixel, rather than using separate integrated circuits. A smart pixel may be based on an integrated stack that includes light emitting elements, an external data contact for receiving digital data for that pixel, and also the pixel pipeline from the digital data to the light emitting elements.