G11B20/1809

Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 3/15 and 4096-symbol mapping, and bit interleaving method using same

A bit-interleaved coded modulation (BICM) reception device and a BICM reception method are disclosed herein. The BICM reception device includes a demodulator, a bit deinterleaver, and a decoder. The demodulator performs demodulation corresponding to 4096-symbol mapping. The bit deinterleaver performs group-unit deinterleaving on interleaved values. The interleaved values are generated after the demodulation. The decoder restores information bits by LDPC-decoding deinterleaved values generated based on the group-unit deinterleaving. The deinterleaved values corresponds to a LDPC codeword having a length of 64800 and a code rate of 3/15.

Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 2/15 and 1024-symbol mapping, and bit interleaving method using same

A bit-interleaved coded modulation (BICM) reception device and a BICM reception method are disclosed herein. The BICM reception device includes a demodulator, a bit deinterleaver, and a decoder. The demodulator performs demodulation corresponding to 1024-symbol mapping. The bit deinterleaver performs group-unit deinterleaving on interleaved values. The interleaved values are generated after the demodulation. The decoder restores information bits by LDPC-decoding deinterleaved values generated based on the group-unit deinterleaving. The deinterleaved values corresponds to a LDPC codeword having a length of 64800 and a code rate of 2/15.

Codeword interleaving for magnetic storage media
11061582 · 2021-07-13 · ·

The present disclosure describes aspects of codeword interleaving for magnetic storage media. In some aspects, segments of a codeword are spread or interleaved across multiple sectors of magnetic storage media. Data for one or more codewords may be received by a read channel and, for each codeword, a respective indicator is selected or received. The indicator may indicate which partitions of the multiple sectors that segments of one of the codewords are to be written. The data is then encoded to provide the codewords and segments of the codewords are placed in an interleaver based on the respective indicator corresponding to the codeword. The codeword segments are written from the interleaver to partitions of the multiple sectors of the magnetic storage media. By so doing, codewords may be spread across multiple sectors, such that a loss of a few sectors does not prevent readback and decoding of the codewords.

Codeword Interleaving for Magnetic Storage Media
20200272339 · 2020-08-27 · ·

The present disclosure describes aspects of codeword interleaving for magnetic storage media. In some aspects, segments of a codeword are spread or interleaved across multiple sectors of magnetic storage media. Data for one or more codewords may be received by a read channel and, for each codeword, a respective indicator is selected or received. The indicator may indicate which partitions of the multiple sectors that segments of one of the codewords are to be written. The data is then encoded to provide the codewords and segments of the codewords are placed in an interleaver based on the respective indicator corresponding to the codeword. The codeword segments are written from the interleaver to partitions of the multiple sectors of the magnetic storage media. By so doing, codewords may be spread across multiple sectors, such that a loss of a few sectors does not prevent readback and decoding of the codewords.

BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 3/15 AND 4096-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 4096-symbol mapping.

BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 2/15 AND 1024-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 1024-symbol mapping.

Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 3/15 and 4096-symbol mapping, and bit interleaving method using same

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 3/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 4096-symbol mapping.

Bit interleaver for low-density parity check codeword having length of 64800 and code rate of 2/15 and 1024-symbol mapping, and bit interleaving method using same

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 1024-symbol mapping.

Sequential data storage with rewrite using dead-track detection

A system includes, according to one embodiment, a magnetic head having a plurality of write transducers configured to store data to tracks of a sequential access medium and a plurality of read transducers. Each read transducer is configured to read data from the sequential access medium after being written thereto by a corresponding write transducer. A first of the read transducers is aligned with a first of the write transducers, wherein the output of the first read transducer is produced during read-while-write. The system also includes a controller and logic integrated with and/or executable by the controller. The logic is configured to read, using the plurality of read transducers, encoded data from a plurality of tracks of the sequential access medium simultaneously. The logic is configured to determine that one or more tracks of the sequential access medium are dead within a sliding window and rewrite a set of encoded data from the one or more dead tracks to one or more live tracks in a rewrite area of the sequential access medium. Other systems, methods, and computer program products are described according to more embodiments.

BIT INTERLEAVER FOR LOW-DENSITY PARITY CHECK CODEWORD HAVING LENGTH OF 64800 AND CODE RATE OF 2/15 AND 1024-SYMBOL MAPPING, AND BIT INTERLEAVING METHOD USING SAME

A bit interleaver, a bit-interleaved coded modulation (BICM) device and a bit interleaving method are disclosed herein. The bit interleaver includes a first memory, a processor, and a second memory. The first memory stores a low-density parity check (LDPC) codeword having a length of 64800 and a code rate of 2/15. The processor generates an interleaved codeword by interleaving the LDPC codeword on a bit group basis. The size of the bit group corresponds to a parallel factor of the LDPC codeword. The second memory provides the interleaved codeword to a modulator for 1024-symbol mapping.