A non-volatile memory device, described herein, comprises: a plurality of memory strings and at least one control circuit in communication with the non-volatile memory cell array. The at least one control circuit is configured to perform, for the plurality of memory strings, one erase-verify iteration in an erase operation including determining whether at least one memory string of the plurality of memory strings passes an erase-verify test. The at least one control circuit is configured to, if the at least one memory string passes the erase-verify test, inhibit the at least one memory string for erase including ramping up, to an erase voltage, of a voltage applied to a gate of a SGD transistor of the at least one memory string and to perform a next erase-verify iteration in the erase operation for remaining memory strings of the plurality of memory strings other than the at least one memory string.

A memory apparatus and method of operation are provided. The apparatus includes apparatus including memory cells connected to word lines including at least one dummy word line and data word lines. The memory cells are arranged in strings and are configured to retain a threshold voltage. The apparatus also includes a control means coupled to the word lines and the strings and configured to identify ones of the memory cells connected to the at least one dummy word line with the threshold voltage being below a predetermined detection voltage threshold following an erase operation. The control means is also configured to selectively apply at least one programming pulse of a maintenance program voltage to the at least one dummy word line to program the ones of the memory cells connected to the at least one dummy word line having the threshold voltage being below the predetermined detection voltage threshold.

An electronic device, and an over-erase detection and elimination method for memory cells are provided; the method includes: performing an erase operation on a specified area; selecting all the memory cells in the selected area one by one; measuring a threshold voltage of a selected memory cell for over-erase detection to see if it is less than a normal erase threshold voltage; if not, selecting the next memory cell for over-erase detection, and if yes, then performing a soft-write operation on the selected memory cell; after the soft-write operation, performing over-erase detection again to see whether the threshold voltage of the selected memory cell is within a normal threshold range; and if not, performing a soft-write operation again, and if yes, the next memory cell is selected for over-erase detection, until the threshold voltages of all the memory cells selected for erasure are within the normal threshold range.

Provided is a memory device including a memory structure including a substrate, a channel region, first and second doped regions, a floating gate and a dielectric layer. The channel region is disposed on the substrate. The first and the second doped regions are disposed on the substrate and respectively located at two sides of the channel region. The floating gate is disposed on the channel region. The dielectric layer is disposed between the floating gate and the channel region, the first doped region and the second doped region. The floating gate and the first doped region are partially overlapped, and/or the floating gate and the second doped region are not overlapped and a sidewall of the floating gate adjacent to the second doped region and a boundary between the second doped region and the channel region are separated by a distance.

A memory apparatus and method of operation is provided. The apparatus includes memory cells connected to word lines and bit lines and arranged in strings and configured to retain a threshold voltage. Each of the memory cells is configured to be erased in an erase operation occurring during an erase time period. A control circuit is configured to adjust at least a portion of the erase time period in response to determining the erase operation is a segmented erase operation and is resumed after being suspended. The control circuit applies an erase signal having a plurality of voltage segments temporally separated from one another during the erase time period to each of the strings while simultaneously applying a word line erase voltage to selected ones of the word lines to encourage erasing of the memory cells coupled to the selected ones of the word lines in the segmented erase operation.

A non-volatile memory device includes a plurality of cell strings in a vertical direction, each of the plurality of cell strings including a plurality of memory cells respectively connected to a plurality of word lines, and an erase control transistor having a first end connected to at least one of both ends of plurality of memory cells and a second end connected to at least one of both ends of each of the plurality of cell strings, and a row decoder configured to apply a first bias voltage to the plurality of word lines in a first period in which an erase voltage applied to the second end of the erase control transistor increases to a target level and to apply a second bias voltage higher than the first bias voltage to at least some of the plurality of word lines in a second period after the first period.

A memory storage device including a flash memory and a controller circuit is provided. The flash memory includes a plurality of memory cells. Each of the memory cells includes a substrate, a drain terminal, a source terminal, and a gate terminal. The controller circuit is coupled to the flash memory. The controller circuit is configured to perform a first erase operation on the memory cells to obtain a first erase threshold voltage distribution, and perform a program operation on the memory cells to obtain a program threshold voltage distribution. The first erase threshold voltage distribution is larger than a first target voltage. The program threshold voltage distribution is smaller than a second target voltage. The first target voltage is larger than the second target voltage. A writing method of a flash memory is also provided.

A memory device and associated techniques provide a uniform erase depth for different blocks of memory cells which are at different distances from pass gates of a voltage source. In one approach, a voltage of a source side select gate transistor of a memory string is a decreasing function of the distance. In another approach, a magnitude or duration of an erase voltage at a source end of a memory string is an increasing function of the distance. Adjacent blocks can be arranged in subsets and treated as being at a common distance. In another approach, an additional erase pulse can be applied when the distance of the block exceeds a threshold. Other variables such as initial erase voltage and step size can also be adjusted as a function of distance.

The invention provides a storage structure and an erase method thereof, which can perform an erase operation on memory blocks B.sub.1 . . . B.sub.n, where n is an integer greater than or equal to 2. The storage structure includes a first memory bank, a second memory bank and a controller, wherein the memory blocks are sequentially alternately arranged in the first memory bank and the second memory bank. The controller is used to control the memory blocks to sequentially undergo an erase operation. The erase operation includes sequentially performing a first process and a second process. When memory block B.sub.i undergoes the second process, the memory block B.sub.i+1 undergoes the first process, where i ∈ [1, n−1].

A nonvolatile memory device includes a memory cell array having memory cells, a row decoder circuit connected to the memory cells through word lines, a page buffer circuit connected to the memory cells through bit lines, and a control circuit controlling the row decoder circuit and the page buffer circuit to repeatedly perform an erase loop including an erase and an erase verification with respect to the memory cells. The control circuit is configured to select one of an increase and a decrease of an erase voltage according to a result of the erase verification of a current erase loop and apply the controlled erase voltage to the memory cells in the erase operation of a subsequent erase loop.