A precharging circuit, a scanning driving circuit, an array substrate, and a display device are provided. The precharging circuit includes an input end, an output end, and further includes a switching unit, first pull-up unit, and second pull-up unit. The switching unit has first end connected to first node; second end connected to the input end, and third end connected to second node, and is used for conducting the second end and the third end when first end is at high level; first pull-up unit has first end connected to the output end and second end connected to first node, and is used for pulling up potential of second end when first end is at high level; second pull-up unit has first end connected to second node and second end connected to output end, is used for pulling up potential of second end when first end is at high level.

A shift register unit and a control method thereof, a gate drive device including the shift register unit, and a display device. The shift register unit includes: an input module, a pull-up module, a first pull-down control signal generation module, controlling, in the period that a first signal is high level, potential of a first pull-down control node according to a drive input signal and potential of a pull-up control node; a second pull-down control signal generation module, controlling, in the period that a second signal is high level, potential of a second pull-down control node according to the drive input signal and the potential of the pull-up control node, the first signal and the second signal alternatively becoming high level; and a pull-down module, pulling down a drive output signal according to the potential of the first pull-down control node and the potential of the second pull-down control node.

Disclosed are a shift register unit, an operation method therefor and a shift register including the shift register unit. The shift register unit includes: an input module configured to transmit a received input signal to a pull-up node; an output module configured to output a first control signal of a first control signal end to an output end when a pull-up signal at the pull-up node is at an effective pull-up level; and a coupling module having a first end connected to a second control signal end and a second end connected to the pull-up node, and being configured to control the pull-up signal at the pull-up node in a voltage coupling manner according to a second control signal of the second control signal end. By further pulling up the voltage at the pull-up node when output end is reset, the speed of resetting the output end can be increased.

The present disclosure provides a shift register, including: an input circuit, electrically connected to a triggering signal line that provides a triggering signal, a first clock signal line that provides a first clock signal, and a first node; configured for controlling whether the triggering signal is outputted to the first node based on the first clock signal; a control circuit, electrically connected to the first node, a second node, the first clock signal line, a second clock signal line that provides a second clock signal, and a turn-on signal line that provides a turn-on signal, configured for controlling whether the turn-on signal is outputted to the second node; and an output circuit, electrically connected to the first node, the second node, a first signal line that provides a first signal, a second signal line that provides a second signal, and a driving signal output line that outputs a driving signal.

A marching memory is disclosed having an array of memory units. Each memory unit has a sequence of bit level cells. Each bit-level cell has a transfer-transistor having a first main-electrode connected to a clock signal supply line through a first delay element, and a control-electrode connected to an output terminal of a first neighboring bit-level cell positioned at an input side of the array of the memory units, through a second delay element. Each bit-level cell also has a reset-transistor having a first main-electrode connected to a second main-electrode of the transfer-transistor, a control-electrode connected to the clock signal supply line, and a second main-electrode connected to the ground potential. Each bit-level cell also has a capacitor connected in parallel with the reset-transistor.

A gate driver (scanning signal line drive circuit) that can allow a gate output to promptly fall without causing a deterioration in a transistor is implemented. A gate-output fall transistor (T01) and a gate-output stabilization transistor (T02) are provided near an output portion of the unit circuit that constitutes a shift register. A first gate low voltage (Vgl1) having a voltage level that is conventionally used to bring pixel TFTs into an off state is provided to a source terminal of the gate-output stabilization transistor (T02), and a second gate low voltage (Vgl2) having a lower voltage level than the first gate low voltage (Vgl1) is provided to a source terminal of the gate-output fall transistor (T01). Upon allowing the gate output to fall, the gate-output fall transistor (T01) is brought into an on state and then the gate-output stabilization transistor (T02) is brought into an on state.

A memory array comprises a data block comprising N serially connected cells. Each cell of the cells comprises a memory element storing a respective bit of the word, a charge adding unit and a switching logic. The last cell of the cells is further configured to receive a sequence of M bits. The memory array further comprises an output block serially connected to the data block. The output block comprises a result accumulation unit. The memory array is configured to operate in accordance with a 3-phase clocking scheme having a sequence of M groups of clock cycles associated with the respective sequence of M bits. The memory array is configured such that a successive and repetitive application of the three phases enables an application of a phase during each clock cycle of the M groups.

A marching memory is disclosed having an array of memory units. Each memory unit has a sequence of bit level cells. Each bit-level cell has a transfer-transistor having a first main-electrode connected to a clock signal supply line through a first delay element, and a control-electrode connected to an output terminal of a first neighboring bit-level cell positioned at an input side of the array of the memory units, through a second delay element. Each bit-level cell also has a reset-transistor having a first main-electrode connected to a second main-electrode of the transfer-transistor, a control-electrode connected to the clock signal supply line, and a second main-electrode connected to the ground potential. Each bit-level cell also has a capacitor connected in parallel with the reset-transistor.

A gate driver (scanning signal line drive circuit) that can allow a gate output to promptly fall without causing a deterioration in a transistor is implemented. A gate-output fall transistor (T01) and a gate-output stabilization transistor (T02) are provided near an output portion of the unit circuit that constitutes a shift register. A first gate low voltage (Vgl1) having a voltage level that is conventionally used to bring pixel TFTs into an off state is provided to a source terminal of the gate-output stabilization transistor (T02), and a second gate low voltage (Vgl2) having a lower voltage level than the first gate low voltage (Vgl1) is provided to a source terminal of the gate-output fall transistor (T01). Upon allowing the gate output to fall, the gate-output fall transistor (T01) is brought into an on state and then the gate-output stabilization transistor (T02) is brought into an on state.

The present disclosure provides a display device including a display panel and a scan driver. The display panel displays an image. The scan driver includes a scan signal generation circuit disposed on one side of the display panel, and an emission signal generation circuit disposed on the other side of the display panel. The emission signal generation circuit outputs an emission signal having at least two Logic High sections in response to an external clock signal and a first scan signal output from the scan signal generation circuit.