An array device and a writing method thereof are provided. A synapse array device includes: a crossbar array, in which a resistive memory element is connected to each intersection of a plurality of row lines and a plurality of column lines; a row select/drive circuit selecting a row line of the crossbar array and applying a pulse signal to the selected row line; a column select/drive circuit selecting a column line of the crossbar array and applying a pulse signal to the selected column line; and a writing part writing to the resistive memory element connected to the selected row line and the selected column line. A first write voltage with controlled pulse width is applied to the selected row line, and a second write voltage with controlled pulse width is applied to the selected column line to perform set writing of the resistive memory element.

An array device and a writing method thereof are provided. A synapse array device includes: a crossbar array, in which a resistive memory element is connected to each intersection of a plurality of row lines and a plurality of column lines; a row select/drive circuit selecting a row line of the crossbar array and applying a pulse signal to the selected row line; a column select/drive circuit selecting a column line of the crossbar array and applying a pulse signal to the selected column line; and a writing part writing to the resistive memory element connected to the selected row line and the selected column line. A first write voltage with controlled pulse width is applied to the selected row line, and a second write voltage with controlled pulse width is applied to the selected column line to perform set writing of the resistive memory element.

An embodiment method for programming a differential type phase-change memory device comprises, in a first time interval, programming a direct memory cell or the respective complementary one pertaining to a first programming driver by means of a current between SET and RESET; and, in the same first time interval, simultaneously programming a direct memory cell or the respective complementary one pertaining to a second programming driver by means of the same current between SET and RESET. The method further comprises, in a second time interval, programming the other direct memory cell or the respective complementary one pertaining to the first programming driver by means of the other current between SET and RESET; and, in the same second time interval, simultaneously programming the other direct memory cell or the respective complementary one pertaining to the second programming driver by means of the same other current between SET and RESET.

Memory devices and memory operational methods are described. One example memory system includes a common conductor and a plurality of memory cells coupled with the common conductor. The memory system additionally includes access circuitry configured to provide different ones of the memory cells into one of a plurality of different memory states at a plurality of different moments in time between first and second moments in time. The access circuitry is further configured to maintain the common conductor at a voltage potential, which corresponds to the one memory state, between the first and second moments in time to provide the memory cells into the one memory state.

A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The memory structure includes one or more planes of non-volatile memory cells. Each plane is divided into a plurality of partial planes. The control circuit is configured to write to and read from the memory cells by writing a partial page into a particular partial plane and reading the partial page from the particular partial plane using a set of parameters optimized for the particular partial plane.

An embodiment method for programming a differential type phase-change memory device comprises, in a first time interval, programming a direct memory cell or the respective complementary one pertaining to a first programming driver by means of a current between SET and RESET; and, in the same first time interval, simultaneously programming a direct memory cell or the respective complementary one pertaining to a second programming driver by means of the same current between SET and RESET. The method further comprises, in a second time interval, programming the other direct memory cell or the respective complementary one pertaining to the first programming driver by means of the other current between SET and RESET; and, in the same second time interval, simultaneously programming the other direct memory cell or the respective complementary one pertaining to the second programming driver by means of the same other current between SET and RESET.

A memory apparatus and a data access method for a memory are provided. The data access method includes: receiving a data erase command for performing a data erase operation; and, during the data erase operation: configuring a selected memory cell block in the memory according to the data erase command; providing a flag memory cell corresponding to the selected memory cell block, erasing a data in the flag memory cell according to the data erase command, and keeping a data in a plurality of selected memory cells in the selected memory cell block unchanged.

In a method of writing data in a nonvolatile memory device including a plurality of cell strings, each of the plurality of cell strings includes a plurality of memory cells disposed in a vertical direction. A program target page is divided into a plurality of subpages. The program target page is connected to one of a plurality of wordlines. Each of the plurality of subpages includes memory cells that are physically spaced apart from one another. A program operation is sequentially performed on the plurality of subpages. A program verification operation is performed on the program target page including the plurality of subpages at a time.

A method for programming a resistive random access memory including a matrix of memory cells. This method includes a programming procedure that includes applying a programming voltage ramp to the memory cells of a part at least of the matrix, the programming voltage ramp starting at a first non-zero voltage value, called start voltage, and ending at a second voltage value, called stop voltage, greater in absolute value than the first voltage value. The stop voltage is determined such that each memory cell of said at least one part of the matrix has a first probability between 1/(10N) and 1/N of having a programming voltage greater in absolute value than the stop voltage (V.sub.stop), N being the number of memory cells in the at least one part of the matrix.

A non-volatile memory system comprises a memory structure and a control circuit connected to the memory structure. The memory structure includes one or more planes of non-volatile memory cells. Each plane is divided into a plurality of partial planes. The control circuit is configured to write to and read from the memory cells by writing a partial page into a particular partial plane and reading the partial page from the particular partial plane using a set of parameters optimized for the particular partial plane.