A phase-change memory (10) for the non-volatile storage of binary contents stores the binary contents electrically and/or optically in a non-volatile manner by locally switching a material (18) between an amorphous and a crystalline phase. The state with respect to the electrical conductivity of the material (18) and/or the reflection properties of the material (18) determines the information content of the phase-change memory (10). A method for non-volatile storage of binary contents in a phase-change memory (10), which stores the binary contents electrically and/or optically in a non-volatile manner by locally switching a material (18) between an amorphous and a crystalline phase, whereby the state with respect to the electrical conductivity of the material (18) and/or the reflection properties of the material (18) determines the information content of the phase-change memory (10).

A phase-change memory (10) for the non-volatile storage of binary contents stores the binary contents electrically and/or optically in a non-volatile manner by locally switching a material (18) between an amorphous and a crystalline phase. The state with respect to the electrical conductivity of the material (18) and/or the reflection properties of the material (18) determines the information content of the phase-change memory (10). A method for non-volatile storage of binary contents in a phase-change memory (10), which stores the binary contents electrically and/or optically in a non-volatile manner by locally switching a material (18) between an amorphous and a crystalline phase, whereby the state with respect to the electrical conductivity of the material (18) and/or the reflection properties of the material (18) determines the information content of the phase-change memory (10).

A semiconductor storage device comprises a plurality of memory cells arranged in a matrix. Each of the memory cells includes: a semiconductor storage element including a silicon carbide substrate and a silicon carbide film on a first surface of the silicon carbide substrate; a lower electrode on a second surface facing away from the first surface of the silicon carbide substrate; and an upper electrode on at least part of a surface of the silicon carbide film, the surface facing away from another surface of the silicon carbide film in contact with the silicon carbide substrate. Each memory cell includes at least one basal plane dislocation formed at at least part of the semiconductor storage element.

A tunable resistive element includes a first terminal, a second terminal and a resistive layer having a tunable resistive material. The resistive layer is arranged between the first terminal and the second terminal. The resistive element further includes a piezoelectric layer having a piezoelectric material. The piezoelectric layer is adapted to apply stress to the resistive layer. An electrical resistance of the tunable resistive material is dependent upon a first electrical control signal applied to the first terminal and the second terminal as well as upon the stress applied by the piezoelectric layer to the resistive layer. The stress applied by the piezoelectric layer is dependent on a second electrical control signal applied to the piezoelectric layer.

A tunable resistive element includes a first terminal, a second terminal and a resistive layer having a tunable resistive material. The resistive layer is arranged between the first terminal and the second terminal. The resistive element further includes a piezoelectric layer having a piezoelectric material. The piezoelectric layer is adapted to apply stress to the resistive layer. An electrical resistance of the tunable resistive material is dependent upon a first electrical control signal applied to the first terminal and the second terminal as well as upon the stress applied by the piezoelectric layer to the resistive layer. The stress applied by the piezoelectric layer is dependent on a second electrical control signal applied to the piezoelectric layer.

An electrical resistor element, system, and method related thereto, wherein the electrical resistor element includes a tunable resistance. The electrical resistor element comprises a first contact electrode, a second contact electrode and a ferroelectric layer arranged between the first contact electrode and the second contact electrode. The ferroelectric layer comprises a first area having a first polarization direction and a second area having a second polarization direction. The first polarization direction is different to the second polarization direction. The ferroelectric layer further comprises a domain wall between the first area and the second area. The electrical resistor element further comprises a first pinning element configured to stabilize the first polarization direction of the ferroelectric layer. The electrical resistor element further comprises a control circuit configured to tune the resistance of the electrical resistor element by applying electrical pulses to the ferroelectric layer such that the ferroelectric domain wall is moved.

A non-volatile memory apparatus includes a first hydrogen reservoir, which is electrically conductive; a charge of hydrogen, which is captured in the first hydrogen reservoir; a dielectric layer that has a first side that is adjacent to the first hydrogen reservoir and a second side that is opposite from the first hydrogen reservoir; a second hydrogen reservoir that is adjacent to the second side of the dielectric layer, is electrically conductive, and has a side that is opposite from the dielectric layer; and a piezoelectric layer that is adjacent to the side of the second hydrogen reservoir and that has a side that is opposite from the second hydrogen reservoir.

A semiconductor storage device comprises a plurality of memory cells arranged in a matrix. Each of the memory cells includes: a semiconductor storage element including a silicon carbide substrate and a silicon carbide film on a first surface of the silicon carbide substrate; a lower electrode on a second surface facing away from the first surface of the silicon carbide substrate; and an upper electrode on at least part of a surface of the silicon carbide film, the surface facing away from another surface of the silicon carbide film in contact with the silicon carbide substrate. Each memory cell includes at least one basal plane dislocation formed at at least part of the semiconductor storage element.

An electrical resistor element, system, and method related thereto, wherein the electrical resistor element includes a tunable resistance. The electrical resistor element comprises a first contact electrode, a second contact electrode and a ferroelectric layer arranged between the first contact electrode and the second contact electrode. The ferroelectric layer comprises a first area having a first polarization direction and a second area having a second polarization direction. The first polarization direction is different to the second polarization direction. The ferroelectric layer further comprises a domain wall between the first area and the second area. The electrical resistor element further comprises a first pinning element configured to stabilize the first polarization direction of the ferroelectric layer. The electrical resistor element further comprises a control circuit configured to tune the resistance of the electrical resistor element by applying electrical pulses to the ferroelectric layer such that the ferroelectric domain wall is moved.

Methods of forming and operating phase change memory devices include adjusting an activation energy barrier between a metastable phase and a stable phase of a phase change material in a memory cell. In some embodiments, the activation energy barrier is adjusted by applying stress to the phase change material in the memory cell. Memory devices include a phase change memory cell and a material, structure, or device for applying stress to the phase change material in the memory cell. In some embodiments, a piezoelectric device may be used to apply stress to the phase change material. In additional embodiments, a material having a thermal expansion coefficient greater than that of the phase change material may be positioned to apply stress to the phase change material.