The present technology may include a first storage circuit connected to a plurality of memory banks, an error correction circuit, a read path including a plurality of sub-read paths connected between the plurality of memory banks and the error correction circuit, and a control circuit configured to control data output from the plurality of memory banks to be simultaneously stored in the first storage circuit by deactivating the read path during a first sub-test section, and to control the data stored in the first storage circuit to be sequentially transmitted to the error correction circuit by sequentially activating the plurality of sub-read paths during a second sub-test section.

Methods and apparatus for opportunistic full duplex DRAM for tightly coupled compute die and memory die. A memory controller includes one or more memory channel input-output (IO) interfaces having sets of read data (RdDQ) lines and write data (WrDQ) lines, and includes logic to implement concurrent read and write operations utilizing the RdDQ lines and WrDQ lines. A memory channel IO interface may be coupled to one or more memory devices such as DRAM DIMMs or DRAM/SDRAM dies having a mating IO interface, such as using through-silicon vias (TSVs) and die-to-die interconnects. Circuitry in a memory device or die includes a macro block of IO drivers coupled to the memory channel IO circuitry via a macro interface supporting full duplex operations. IO drivers in a macro block may be connected to memory banks using half-duplex bi-direction links to different banks or full duplex links to the same bank.

A memory chip may include: a plurality of memory banks; a data storage configured to store access information indicative of access operations for one or more segments of the plurality of memory banks; and a refresh controller configured to perform a refresh operation of the one or more segments based, at least in part, on the stored access information.

A request is received to perform a multi-plane operation for data residing on a first plane and a second plane of a memory device. A first set of trim values is obtained from a first set of registers of the memory device. The first set of trim values corresponds to a first voltage shift for the data at the first plane. A second set of trim values is obtained from a second set of registers of the memory device. The second set of trim values corresponds to a second voltage shift for the data at the second set of trim values for the data at the second plane. The multi-plane operation is performed using at least the first set of trim values for the data at the first plane and at least the second set of trim values for the data at the second plane.

Methods, systems, and apparatuses related to memory operation with common clock signals are provided. A memory device or system that includes one or more memory devices may be operable with a common clock signal without a delay from switching on-die termination on or off. For example, a memory device may comprise first impedance adjustment circuitry configured to provide a first impedance to a received clock signal having a clock impedance and second impedance adjustment circuitry configured to provide a second impedance to the received clock signal. The first impedance and the second impedance may be configured to provide a combined impedance about equal to the clock impedance when the first impedance adjustment circuitry and the second impedance adjustment circuitry are connected to the received clock signal in parallel.

In various examples, a test system is provided for executing built-in-self-test (BIST) on integrated circuits deployed in the field. The integrated circuits may include a first device and a second device, the first device having direct access to external memory, which stores test data, and the second device having indirect access to the external memory by way of the first device. In addition to providing a mechanism to permit the first device and the second device to run test concurrently, the hardware and software may reduce memory requirements and runtime associated with running the test sequences, thereby making real-time BIST possible in deployment. Furthermore, some embodiments permit a single external memory image to cater to different SKU configurations.

A write circuit for writing to a plurality of memory cells of a non-volatile data memory, including a buffer memory forming a single memory element which is configured to buffer a first data value before storing said value in the plurality of non-volatile memory cells of the non-volatile data memory. The write circuit also includes a first write line, by means of which the buffer memory is connected to a first memory cell of the plurality of memory cells, and a second write line, which is different from the first write line and by means of which the buffer memory is connected to a second memory cell of the plurality of memory cells. The write circuit further includes a control circuit configured to concurrently write the first data value in the first memory cell and a second data value which depends on the first data value into the second memory cell, wherein the second data value is complementary to the first data value or is identical to the first data value depending on a selected one of a first option or a second option by the control circuit, respectively.

A semiconductor device includes a test command generation circuit that generates a test write command and a test read command when entering a test mode, and an input/output control circuit that controls a memory block, the memory block including a plurality of banks such that write operations are simultaneously performed on the plurality of banks based on the test write command and read operations are simultaneously performed on the plurality of banks based on the test read command.

An apparatus includes a controller adapted to be coupled to memory components in parallel and configured to provide memory address signals and a controller clock signal to the memory components, a memory enable logic circuit coupled to the controller and adapted to be coupled to the memory components in parallel and configured to provide test-enable signals to the memory components. The test-enable signals enable, with the controller clock signal, the memory components to read locally stored memory values. The apparatus includes a multiplexer adapted to be coupled to the memory components in parallel and configured to receive from the memory components memory signals that include the memory values in respective sequences of the memory clock signals, and a pipeline coupled to the multiplexer and the controller and configured to receive the memory values from the multiplexer and send the memory values to a multiple input signature register of the controller.

A test system of embodiments electrically connects one or more first semiconductor chips formed on a first wafer and one or more second semiconductor chips formed on a second wafer to perform tests on the one or more first and second semiconductor chips. The test system includes a test device that supplies a test signal to each of the one or more first semiconductor chips, a first probe device including a first probe to be connected to a first internal pad of each of the one or more first semiconductor chips and a first communication circuit configured to transmit and receive a signal, and a second probe device including a second probe to be connected to a second internal pad of each of the one or more second semiconductor chips and a second communication circuit configured to transmit and receive the signal to and from the first communication circuit.