Plasma processing equipment includes a chuck stage for supporting a wafer and including a lower electrode, an upper electrode disposed on the chuck stage, an AC power supply which applies first to third signals having different magnitudes of frequencies to the upper electrode or the lower electrode, a dielectric ring which surrounds the chuck stage, an edge electrode located within the dielectric ring, and a resonance circuit connected to the edge electrode. The resonance circuit includes a filter circuit which allows only the third signal among the first to third signals to pass, and a series resonance circuit connected in series with the filter circuit and having a first coil and a first variable capacitor connected in series and grounded.

Devices and methods for controlling wafer uniformity using a gas baffle plate are disclosed. In one example, a device for plasma-based processes is disclosed. The device includes: a housing defining a process chamber and a baffle plate arranged above a wafer in the process chamber. The baffle plate is configured to control plasma distribution on the wafer. The baffle plate has a shape of an annulus that comprises a first annulus sector and a second annulus sector. The first annulus sector has a first inner radius. The second annulus sector has a second inner radius that is different from the first inner radius.

Plasma processing equipment includes a chuck stage for supporting a wafer and including a lower electrode, an upper electrode disposed on the chuck stage, an AC power supply which applies first to third signals having different magnitudes of frequencies to the upper electrode or the lower electrode, a dielectric ring which surrounds the chuck stage, an edge electrode located within the dielectric ring, and a resonance circuit connected to the edge electrode. The resonance circuit includes a filter circuit which allows only the third signal among the first to third signals to pass, and a series resonance circuit connected in series with the filter circuit and having a first coil and a first variable capacitor connected in series and grounded.

Devices and methods for controlling wafer uniformity using a gas baffle plate are disclosed. In one example, a device for plasma-based processes is disclosed. The device includes: a housing defining a process chamber and a baffle plate arranged above a wafer in the process chamber. The baffle plate is configured to control plasma distribution on the wafer. The baffle plate has a shape of an annulus that comprises a first annulus sector and a second annulus sector. The first annulus sector has a first inner radius. The second annulus sector has a second inner radius that is different from the first inner radius.

Atomic layer etching (ALE) enables effective filling of small feature structures on semiconductor and other substrates, such as contacts and vias, by bottom-up fill, for example electroless deposition (ELD) of cobalt.

A method for fabricating a layer structure in a trench includes: simultaneously forming a dielectric film containing a Si—N bond on an upper surface, and a bottom surface and sidewalls of the trench, wherein a top/bottom portion of the film formed on the upper surface and the bottom surface and a sidewall portion of the film formed on the sidewalls are given different chemical resistance properties by bombardment of a plasma excited by applying voltage between two electrodes between which the substrate is place in parallel to the two electrodes; and substantially removing the sidewall portion of the film by wet etching which removes the sidewall portion of the film more predominantly than the top/bottom portion according to the different chemical resistance properties.

A plasma processing method is implemented by a plasma processing apparatus including a processing chamber, a lower electrode, a focus ring arranged around the lower electrode, an inner upper electrode arranged to face the lower electrode, an outer upper electrode electrically insulated from the inner upper electrode, a quartz member arranged between the inner and outer upper electrodes and above the focus ring, a gas supply unit for supplying gas to the processing chamber, a first high frequency power supply unit for applying a first high frequency power for plasma generation to the lower electrode or the inner and outer upper electrodes, a first direct current power supply unit for applying a variable first direct current voltage to the outer upper electrode, and a control unit. The method includes the control unit controlling the variable first direct current voltage to reduce an amount of change in a tilt angle.

A method for fabricating a layer structure in a trench includes: simultaneously forming a dielectric film containing a Si—N bond on an upper surface, and a bottom surface and sidewalls of the trench, wherein a top/bottom portion of the film formed on the upper surface and the bottom surface and a sidewall portion of the film formed on the sidewalls are given different chemical resistance properties by bombardment of a plasma excited by applying voltage between two electrodes between which the substrate is place in parallel to the two electrodes; and substantially removing either one of but not both of the top/bottom portion and the sidewall portion of the film by wet etching which removes the one of the top/bottom portion and the sidewall portion of the film more predominantly than the other according to the different chemical resistance properties.

A substrate that includes a first film of a silicon-containing film and a second film having a second aperture formed on the first film is subjected to processing that includes: preparing the substrate; controlling a temperature of the substrate to −30° C. or less; and etching the first film through the second aperture using a plasma formed from a first process gas containing a fluorocarbon gas. By etching the first film through the second aperture, a first aperture of a tapered shape is formed in the first film such that a width of the first aperture gradually decreases toward a bottom of the first aperture.

Fabricating a semiconductor substrate by (a) vertical etching a feature having sidewalls and a depth into one or more layers formed on the semiconductor substrate and (b) depositing an amorphous carbon liner onto the sidewalls of the feature. Steps (a) and optionally (b) are iterated until the vertical etch feature has reached a desired depth. With each iteration of (a), the feature is vertical etched deeper into the one or more layers, while the amorphous carbon liner resists lateral etching of the sidewalls of the feature. With each optional iteration of (b), the deposited amorphous carbon liner on the sidewalls of the feature is replenished.