An electronic component includes a lead frame; a semiconductor chip arranged above the lead frame; and a connection layer sequence arranged between the lead frame and the semiconductor chip, wherein the connection layer sequence includes a first intermetallic layer including gold and indium or gold, indium and tin, a second intermetallic layer including indium and a titanium compound, indium and nickel, indium and platinum or indium and titanium, and a third intermetallic layer including indium and gold.

A device includes a relative temperature detector configured to determine a temperature difference between a device temperature sensed near a switch device and an ambient temperature sensed outside the switch device. The relative temperature detector is configured to generate a relative temperature output signal based on comparing the temperature difference to a relative temperature threshold. A power detector is configured to generate a power level signal based on comparing an indication of switch power of the switch device to a power threshold. The power level signal specifies whether the indication of switch power is above or below the power threshold. A thermal capacity control is configured to disable the switch device based on the power level signal specifying that the indication of switch power is above the power threshold and based on the relative temperature output signal indicating the temperature difference is above the relative temperature threshold.

The present invention relates to a method for producing a metal-ceramic substrate. The method has the following steps: providing a stack containing a ceramic body, a metal foil, and a solder material in contact with the ceramic body and the metal foil, wherein the solder material has: a metal having a melting point of at least 700° C., a metal having a melting point of less than 700° C., and an active metal; and heating the stack, wherein at least one of the following conditions is satisfied: the high temperature heating duration is no more than 60 min; the peak temperature heating duration is no more than 30 min; the heating duration is no more than 60 min.

A process for batch fabrication of circuit components is disclosed via simultaneously packaging multiple circuit component dice in a matrix. Each die has electrodes on its tops and bottom surfaces to be electrically connected to a corresponding electrical terminal of the circuit component it's packaged in. For each circuit component in the matrix, the process forms preparative electrical terminals on a copper substrate. Component dice are pick-and-placed onto the copper substrate with their bottom electrodes landing on corresponding preparative electrical terminal. Horizontal conductor plates are then placed horizontally on top of the circuit component dice, with bottom surface at one end of each plate landing on the dice's top electrode. An opening is formed at the opposite end and has vertical conductive surfaces. A vertical conductor block is placed into the opening and lands on the preparative electrical terminal, and the opening's vertical conductive surfaces facing the top end side surface of the vertical block. A thermal reflow then simultaneously melts pre-applied soldering material so that each circuit component die and its vertical conductor block are soldered to the copper substrate below and its horizontal conductor plate above.

A method can include coupling a semiconductor chip and an electrode with a substrate. Bottom and top mold die can be use, where the top mold die define a first space and a second space that is separated from the first space. The method can include injecting encapsulation material to form an encapsulation member coupled to and covering at least a portion of the substrate. The encapsulation member can include a housing unit housing the electrode. The electrode can have a conductive sidewall exposed to, and not in contact with the encapsulation member, such that there is open space between the conductive sidewall of the electrode and the encapsulation member from an uppermost surface to a bottommost surface of the encapsulation member, the substrate can having a portion exposed within the open space, and the encapsulation member can have an open cross-section perpendicular to an upper surface of the substrate.

A semiconductor device includes a conductive substrate, a conductive first joint portion arranged on the substrate, a SiC diode chip arranged on the first joint portion, a conductive second joint portion arranged on the SiC diode chip, and a transistor chip arranged on the second joint portion. The SiC diode chip includes a cathode pad arranged on one end and an anode pad arranged on the other end in the thickness direction. The cathode pad is joined to the substrate by the first joint portion. The transistor chip includes a drain electrode arranged on one end in the thickness direction. The anode pad is joined with the drain electrode by the second joint portion. The anode pad is arranged in a region enclosed by an outer edge of the SiC diode chip as viewed in a thickness direction of the substrate. The anode pad has an area larger than that of the transistor chip as viewed in the thickness direction of the substrate.

Provided is a solder transfer sheet which is capable of increasing the amount of solder to be transferred without the occurrence of bridging. A solder transfer sheet 1A includes a base material 5, an adhesive layer 4 formed on the surface of the base material 5, a solder powder-containing adhesive layer 3 formed on the surface of the adhesive layer 4, and a solder powder layer 2 formed on the surface of the solder powder-containing adhesive layer 3. In the solder powder layer 2, particles of solder powder 20 are arranged in a one-layer sheet form. In the solder powder-containing adhesive layer 3, solder powder 30 and an adhesive component 31 are mixed so as to have such a thickness that two or more layers of the solder powder 30 are stacked.

A method includes obtaining an active feature layer having a first surface bearing one or more active feature areas. A first capacitor plate of a first capacitor is formed on an interior surface of a cap. A second capacitor plate of the first capacitor is formed on an exterior surface of the cap. The first capacitor plate of the first capacitor overlays and is spaced apart from the second capacitor plate of the first capacitor along a direction that is orthogonal to the exterior surface of the cap to form the first capacitor. The cap is coupled with the first surface of the active feature layer such that the second capacitor plate of the first capacitor is in electrical communication with at least a first active feature of the active feature layer. The cap is bonded with the passive layer substrate.

A method includes obtaining an active feature layer having a first surface bearing one or more active feature areas. A first capacitor plate of a first capacitor is formed on an interior surface of a cap. A second capacitor plate of the first capacitor is formed on an exterior surface of the cap. The first capacitor plate of the first capacitor overlays and is spaced apart from the second capacitor plate of the first capacitor along a direction that is orthogonal to the exterior surface of the cap to form the first capacitor. The cap is coupled with the first surface of the active feature layer such that the second capacitor plate of the first capacitor is in electrical communication with at least a first active feature of the active feature layer. The cap is bonded with the passive layer substrate.

Disclosed is a fan-out back-to-back chip stacked package, comprising a back-to-back stack of a first chip and a second chip, an encapsulant, a plurality of vias disposed in the encapsulant, a first redistribution layer and a second redistribution layer. The encapsulant encapsulates the sides of the first chip and the sides of the second chip simultaneously and has a thickness not greater than the chip stacked height to expose a first active surface of the first chip and a second active surface of the second chip. The encapsulant has a first peripheral surface expanding from the first active surface and a second peripheral surface expanding from the second active surface. The first redistribution layer is formed on the first active surface and extended onto the first peripheral surface to electrically connect the first chip to the vias in the encapsulant. The second RDL is formed on the second active surface and extended onto the second peripheral surface to electrically connect the second chip to the vias in the encapsulant. Accordingly, the structure realizes a thin package configuration of multi-chip back-to-back stacking to reduce package warpage.