H01L2021/6006

Fan-out package structure and method

A method comprises embedding a semiconductor structure in a molding compound layer, depositing a plurality of photo-sensitive material layers over the molding compound layer, developing the plurality of photo-sensitive material layers to form a plurality of openings, wherein a first portion and a second portion of an opening of the plurality of openings are formed in different photo-sensitive material layers and filling the first portion and the second portion of the opening with a conductive material to form a first via in the first portion and a first redistribution layer in the second portion.

Fan-Out Package Structure and Method
20210391242 · 2021-12-16 ·

A method comprises embedding a semiconductor structure in a molding compound layer, depositing a plurality of photo-sensitive material layers over the molding compound layer, developing the plurality of photo-sensitive material layers to form a plurality of openings, wherein a first portion and a second portion of an opening of the plurality of openings are formed in different photo-sensitive material layers and filling the first portion and the second portion of the opening with a conductive material to form a first via in the first portion and a first redistribution layer in the second portion.

Three dimensional integrated circuits stacking approach

A semiconductor package and a method of forming a semiconductor package with one or more dies over an interposer are provided. In some embodiments, the semiconductor package has a plurality of through substrate vias (TSVs) extending through an interposer substrate. A redistribution structure is arranged over a first surface of the interposer substrate, and a first die is bonded to the redistribution structure. An edge of the first die is beyond a nearest edge of the interposer substrate. A second die is bonded to the redistribution structure. The second die is laterally separated from the first die by a space.

SEMICONDUCTOR DEVICE WITH OPEN CAVITY AND METHOD THEREFOR
20230268304 · 2023-08-24 ·

A method of forming a semiconductor device is provided. The method includes placing a semiconductor die on a carrier substrate and placing a sacrificial blank on the carrier substrate with a routing structure attached to the sacrificial blank. At least a portion of the semiconductor die, sacrificial blank, and routing structure are encapsulated with an encapsulant. The carrier substrate is separated from a first side of the encapsulated semiconductor die, sacrificial blank, and routing structure to expose a surface of the sacrificial blank. The sacrificial blank is etched to form a cavity in the encapsulant and expose a portion of the routing structure exposed through the cavity.

Electronic apparatus

The disclosure provides an electronic apparatus. The electronic apparatus includes a substrate, a first metal layer, an insulating layer, a first conductor, an electronic assembly and a transistor circuit die. The first metal layer is disposed on the substrate. The insulating layer is disposed on the substrate. The first conductor is formed in a first via of the insulating layer. The electronic assembly is disposed on the substrate and electrically connected to the first metal layer through the first conductor. The transistor circuit die is electrically connected to the first metal layer.

Method of Forming Semiconductor Packages Having Through Package Vias
20230378075 · 2023-11-23 ·

A semiconductor device and method for forming the semiconductor device is provided. The semiconductor device includes an integrated circuit having through vias adjacent to the integrated circuit die, wherein a molding compound is interposed between the integrated circuit die and the through vias. The through vias have a projection extending through a patterned layer, and the through vias may be offset from a surface of the patterned layer. The recess may be formed by selectively removing a seed layer used to form the through vias.

Integrated Circuit Packages and Methods of Forming the Same
20230387101 · 2023-11-30 ·

In an embodiment, a method of forming an integrated circuit package includes: attaching a first carrier to a package component, the package component comprising: an interposer; a first semiconductor die attached to a first side of the interposer; a second semiconductor die attached to the first side of the interposer; an encapsulant encapsulating the first semiconductor die and the second semiconductor die; and conductive connectors attached to a second side of the interposer; attaching a second carrier to a package substrate, the package substrate comprising bond pads; bonding the conductive connectors of the package component to the bond pads of the package substrate by reflowing the conductive connectors while the first carrier is attached to the package component and while the second carrier is attached to the package substrate; removing the first carrier; and removing the second carrier.

ELECTROMAGNETIC WAVE ADJUSTMENT APPARATUS

The disclosure provides an electromagnetic wave adjustment apparatus includes a control circuit, a transistor circuit die and an electronic assembly. The transistor circuit die receives a control signal from the control circuit and drives the electronic assembly.

ELECTRONIC APPARATUS

The disclosure provides an electronic apparatus. The electronic apparatus includes a substrate, a first metal layer, an insulating layer, a first conductor, an electronic assembly and a transistor circuit die. The first metal layer is disposed on the substrate. The insulating layer is disposed on the substrate. The first conductor is formed in a first via of the insulating layer. The electronic assembly is disposed on the substrate and electrically connected to the first metal layer through the first conductor. The transistor circuit die is electrically connected to the first metal layer.

ELECTRONIC APPARATUS AND MANUFACTURING METHOD THEREOF

The disclosure provides an electronic apparatus and a manufacturing method thereof. The electronic apparatus includes a first insulating layer, a first metal layer, a second metal layer, and an electronic assembly. The first insulating layer includes a first surface and a second surface opposite to the first surface. The first metal layer has an opening and is formed on the first surface. The second metal layer is formed on the second surface and a projection of the opening on the second surface is overlapped with a projection of the second metal layer on the second surface. The electronic assembly is electrically connected with the first metal layer and the second metal layer.