A package structure includes a molding material, at least one through-via, at least one conductor, at least one dummy structure and an underfill. The through-via extends through the molding material. The conductor is present on the through-via. The dummy structure is present on the molding material and includes a dielectric material. The underfill is at least partially present between the conductor and the dummy structure.

A package structure includes a molding material, at least one through-via, at least one conductor, at least one dummy structure and an underfill. The through-via extends through the molding material. The conductor is present on the through-via. The dummy structure is present on the molding material and includes a dielectric material. The underfill is at least partially present between the conductor and the dummy structure.

A bonded assembly may be formed by: providing a substrate and a semiconductor chip in a low-oxygen ambient having an oxygen partial pressure that is lower than 17 kPa; disposing the semiconductor chip on the substrate; performing a plasma treatment process on a copper-containing surface of a chip bonding pad on the semiconductor chip in the low-oxygen ambient by directing a plasma jet to the chip bonding pad; and attaching a bonding wire to the semiconductor chip and to the substrate such that a first end of the bonding wire is attached to the copper-containing surface and a second end of the bonding wire is attached to a substrate bonding pad on the substrate.

A molded interconnecting substrate has an embedded redistribution layer (RDL), an embossed RDL, a plurality of conductive pillars encapsulated in a molding core, and a chip also encapsulated in the molded core. The conductive pillars are disposed on the external pads of the embedded RDL. The chip is die-bonded onto the embedded RDL. The molding core has an external surface and an opposing component-installing surface. The embedded RDL is embedded in the molding core from the external surface. The bottom surface of the embedded RDL is coplanar to the external surface and the pillar-top surfaces of the conductive pillars are coplanar to the component-installing surface. The embossed RDL is disposed on and extruded from the component-installing surface including a plurality of pillar-top pads aligned and bonded to the pillar-top surfaces. Accordingly, it is possible to eliminate a flip-chip molding thickness without manufacture of substrate plating lines where fine-pitch substrate circuitry can be achieved without substrate drilling process.

A semiconductor device having dismantlable structure is provided. The method includes forming a packaged semiconductor die by mounting the semiconductor die onto a package substrate in a flip chip orientation, attaching an interposer substrate over a backside of the semiconductor die, and encapsulating with an encapsulant the semiconductor die and remaining gap region between the package substrate and the interposer substrate. A bond pad of the semiconductor die is interconnected with a conductive trace of the package substrate. The interposer substrate includes a plurality of conductive pads exposed at a top surface and interconnected with the package substrate. A dismantlable structure is attached on the top surface of the interposer substrate. A first region of the dismantlable structure covers the plurality of conductive pads.

The invention provides improved techniques for bonding copper to solder or other types of flip chip devices using a passivation coating on copper. The surface of a substrate is cleaned prior to mounting a flip chip device onto the substrate. The substrate is rinsed to remove residual artifacts remaining on the surface subsequent to the cleaning. Subsequent to the rinsing, a protective coating is applied to the surface of the substrate to produce a coated substrate. Copper pillars with solder caps extending from the flip chip device are bonded to metallic features on the surface of the coated substrate.