A handle substrate for a composite structure comprises a base substrate including an epitaxial layer of silicon on a monocrystalline silicon wafer obtained by Czochralski pulling, a passivation layer on and in contact with the epitaxial layer of silicon, and a charge-trapping layer on and in contact with the passivation layer. The monocrystalline silicon wafer of the base substrate exhibits a resistivity of between 10 and 500 ohm.Math.cm, while the epitaxial layer of silicon exhibits a resistivity of greater than 2000 ohm.Math.cm and a thickness ranging from 2 to 100 microns. The passivation layer is amorphous or polycrystalline. A method is described for forming such a substrate.

The present invention relates to a chamfered silicon carbide substrate which is essentially monocrystalline, and to a corresponding method of chamfering a silicon carbide substrate. A silicon carbide substrate according to the invention comprises a main surface (102), wherein an orientation of said main surface (102) is such that a normal vector ({right arrow over (O)}) of the main surface (102) includes a tilt angle with a normal vector ({right arrow over (N)}) of a basal lattice plane (106) of the substrate, and a chamfered peripheral region (110), wherein a surface of the chamfered peripheral region includes a bevel angle with said main surface, wherein said bevel angle is chosen so that, in more than 75% of the peripheral region, normal vectors ({right arrow over (F)}_i) of the chamfered peripheral region (110) differ from the normal vector of the basal lattice plane by less than a difference between the normal vector of the main surface and the normal vector of the basal lattice plane of the substrate.

The invention relates to a process for manufacturing a composite structure comprising a thin layer made of a first single-crystal material positioned on a support substrate. The process comprises: a step a) of providing a donor substrate (10) composed of the first single-crystal material having a front face (10a) and a back face (10b), a step b) of providing a support substrate (20) having a front face (20a), a back face (20b), an edge (20c) and a first alignment pattern (21) on one of said faces or on the edge, a step c) of heat treatment applied at least to the donor substrate (10), under a controlled atmosphere and at a temperature capable of bringing about a surface reorganization on at least one of the faces (10a, 10b) of said substrate (10), the surface reorganization giving rise to the formation of first steps (13) of nanometric amplitude, which are parallel to a first main axis (P1), a step d) of assembling the donor substrate (10) and the support substrate (20) comprising, before the substrates (10, 20) are brought into contact, an optical alignment, to better than ±0.1°, between a locating mark (12) indicating the first main axis (P1) on the donor substrate (10) and at least one alignment pattern (21, 22) of the support substrate (20), a step e) of transferring a thin layer (100) from the donor substrate (10) onto the support substrate (20).

A semiconductor device according to the present disclosure includes a substrate including a plurality of atomic steps that propagate along a first direction, and a transistor disposed on the substrate. The transistor includes a channel member extending a second direction perpendicular to the first direction, and a gate structure wrapping around the channel member.

The present invention relates to a chamfered silicon carbide substrate which is essentially monocrystalline, and to a corresponding method of chamfering a silicon carbide substrate. A silicon carbide substrate according to the invention comprises a main surface (102), wherein an orientation of said main surface (102) is such that a normal vector ({right arrow over (O)}) of the main surface (102) includes a tilt angle with a normal vector ({right arrow over (N)}) of a basal lattice plane (106) of the substrate, and a chamfered peripheral region (110), wherein a surface of the chamfered peripheral region includes a bevel angle with said main surface, wherein said bevel angle is chosen so that, in more than 75% of the peripheral region, normal vectors ({right arrow over (F)}_i) of the chamfered peripheral region (110) differ from the normal vector of the basal lattice plane by less than a difference between the normal vector of the main surface and the normal vector of the basal lattice plane of the substrate.

A semiconductor device according to the present disclosure includes a substrate including a plurality of atomic steps that propagate along a first direction, and a transistor disposed on the substrate. The transistor includes a channel member extending a second direction perpendicular to the first direction, and a gate structure wrapping around the channel member.

Provided is an indium phosphide substrate having good linearity accuracy of a ridge line where the main surface is in contact with the orientation flat, and a method for producing the indium phosphide substrate. An indium phosphide substrate having a main surface and an orientation flat, wherein a maximum value of deviation is less than 1/1000 of a length of a ridge line where the main surface is in contact with the orientation flat, when a plurality of measurement points are set at intervals of 2 mm from a start point to an end point at the ridge line, except for a length portion of 3 mm inward from both ends of the ridge line, and based on a reference line which is a straight line connecting the start point and the end point, a distance of each measurement point from the reference line is defined as the deviation of each measurement point.

To provide a silicon epitaxial wafer production method and a silicon epitaxial wafer in which the DIC defects can be suppressed, a silicon epitaxial wafer production method is provided, in which an epitaxial layer is grown in a vapor phase on a principal plane of a silicon single crystal wafer. The principal plane is a {110} plane or a plane having an off-angle of less than 1 degree from the {110} plane. The silicon epitaxial wafer production method includes setting a temperature of the silicon single crystal wafer to 1140° C. to 1165° C. and growing the epitaxial layer in the vapor phase at a growth rate of 0.5 μm/min to 1.7 μm/min.

The present invention provides monocrystalline 4H—SiC substrates having a specific orientation of its crystal structure which is set such as to reduce or even eliminate the occurrence of cracks or fissures during mechanical processing, and method of producing same. The monocrystalline 4H—SiC substrate, which has a longitudinal axis and an at least partially curved lateral surface parallel to said longitudinal axis, is characterized in that the crystal structure of the 4H—SiC substrate is oriented with respect to the longitudinal axis such that at each position on the lateral surface of the semi-finished product there is a line segment which is intersected by at least a predetermined minimum number of parallel cleavage planes of the {1010} form per unit length, wherein the line segment is defined by a plane tangent to the lateral surface at said position.

To provide a silicon epitaxial wafer production method and a silicon epitaxial wafer in which the DIC defects can be suppressed, a silicon epitaxial wafer production method is provided, in which an epitaxial layer is grown in a vapor phase on a principal plane of a silicon single crystal wafer. The principal plane is a {110} plane or a plane having an off-angle of less than 1 degree from the {110} plane. The silicon epitaxial wafer production method includes setting a temperature of the silicon single crystal wafer to 1100° C. to 1135° C. and growing the epitaxial layer in the vapor phase at a growth rate of 2.0 μm/min to 3.0 μm/min.