A semiconductor device has a first semiconductor die and second semiconductor die with a conductive layer formed over the first semiconductor die and second semiconductor die. The second semiconductor die is disposed adjacent to the first semiconductor die with a side surface and the conductive layer of the first semiconductor die contacting a side surface and the conductive layer of the second semiconductor die. An interconnect, such as a conductive material, is formed across a junction between the conductive layers of the first and second semiconductor die. The conductive layer may extend down the side surface of the first semiconductor die and further down the side surface of the second semiconductor die. An extension of the side surface of the first semiconductor die can interlock with a recess of the side surface of the second semiconductor die. The conductive layer extends over the extension and into the recess.

Techniques herein include methods for coating a single layer actuator film or multi-layer actuator film on the backside of a wafer. The actuator film includes one or more chemical actuators. Chemical actuators are various molecules, crystals, chemical compounds and other chemical compositions that are capable of imposing directional stress in response to application of an external stimulus on the chemical actuator. The external stimulus can include a particular wavelength of light or polarization of light, or heat (or directed infrared radiation) or load, which can include load-responsive actuation or pressure-responsive actuation.

A wide-gap semiconductor substrate enables formation of a device having low power loss while maintaining high mechanical strength. The wide-gap semiconductor substrate (70) is obtained by placing a wide-gap semiconductor substrate onto a platen (15) disposed in a processing chamber (11) and etching and thinning only a first substrate region (70a), where a device (50) is formed, of the wide-gap semiconductor substrate by means of plasma generated from an etching gas. In the wide-gap semiconductor substrate (70), a connecting portion as a peripheral edge of the first substrate region (70a) connecting to a second substrate region (70b) surrounding the first substrate region (70a) includes an arc portion having a predetermined radius of curvature.

A wafer processing method includes the steps of forming a bonded wafer by bonding one surface of a first wafer which is chambered at an outer peripheral edge and includes a device region and an outer peripheral surplus region, to a second wafer, irradiating a laser beam along the outer peripheral edge of the first wafer and forming an annular modified region, thereby segmenting the first wafer into an outer peripheral annular portion and a central region, bonding an expand tape to the other surface of the first wafer, expanding the expand tape, thereby splitting the first wafer into the outer peripheral annular portion and the central region from the annular modified region as a starting point and breaking off the outer peripheral annular portion from the bonded wafer, and grinding the first wafer from the other surface to a finish thickness.

A method for forming a through-substrate via structure includes providing a substrate and providing a conductive via structure adjacent to a first surface of the substrate. The method includes providing a recessed region on an opposite surface of the substrate towards the conductive via structure. The method includes providing an insulator in the recessed region and providing a conductive region extending along a first sidewall surface of the recessed region in the cross-sectional view. In some examples, the first conductive region is provided to be coupled to the conductive via structure and to be further along at least a portion of the opposite surface of the substrate outside of the recessed region. The method includes providing a protective structure within the recessed region over a first portion of the first conductive region but not over a second portion of the first conductive region that is outside of the recessed region. The method includes attaching a conductive bump to the second portion of the first conductive region.

In certain aspects, a method for controlling wafer stress is disclosed. A semiconductor film is formed on a backside of a wafer. The wafer is deformed by stress associated with a front-side semiconductor structure on a front side of the wafer opposite to the backside of the wafer. A laser application region of the semiconductor film is determined. A laser anneal process is performed in the laser application region of the semiconductor film.

The occurrence of breaking and chipping at the wafer peripheral edge of a bonded wafer obtained by bonding a lamination wafer on a support wafer is suppressed. A lamination wafer to be bonded to a support wafer includes a large-diameter portion made of a silicon wafer whose peripheral edge is chamfered and a small-diameter portion, whose diameter is smaller than that of the large-diameter portion, formed on the large-diameter portion concentrically and integrally with the large-diameter portion, and the small-diameter portion includes a straight body portion whose side surface is perpendicular to the wafer surface, and a neck portion whose side surface is oblique with a predetermined angle to the wafer between the straight body portion and the large-diameter portion, and the small-diameter portion is formed such that the upper face of the straight body portion is to be bonded to the support wafer.

The present invention provides an ASC process automation device including: a loading part into which an ingot having been subjected to a wire sawing is input; a kerosene cleaning part for cleaning the ingot with kerosene; a precleaning part for precleaning the ingot; a main cleaning part for cleaning the ingot multiple times; a wafer peeling part for peeling the ingot to produce multiple wafers; and a transport unit for moving the ingot linearly and upward/downward while proceeding to the kerosene cleaning part, the precleaning part, the main cleaning part, and the wafer peeling part.

The present disclosure relates to a semiconductor packaging method. The method includes: providing a first wafer; and performing a wafer stacking operation a plurality of times. The wafer stacking operation includes: forming a first to-be-bonded wafer in the shape of a boss, where the first to-be-bonded wafer includes a base and a protrusion from the base, and orientating the protrusion toward a second to-be-bonded wafer and bonding the protrusion to the second to-be-bonded wafer; forming a first dielectric layer on a surface of the protrusion; and performing second trimming on an edge region of the protrusion and an edge region of the second to-be-bonded wafer, so that the remainder of the second to-be-bonded wafer after the second trimming is in the shape of a boss, and using the remainder of the wafer stack after the second trimming as the first to-be-bonded wafer for next wafer stacking.

In accordance with the following step of a method of manufacturing a MOSFET, a first cutting step of cutting a silicon carbide wafer along a plane substantially parallel to a {11-20} plane is performed. After the first cutting step, a second cutting step of cutting the silicon carbide wafer along a plane substantially perpendicular to the {11-20} plane and substantially perpendicular to the first main surface is performed.