A nitride semiconductor device includes an electron transit layer (103) that is formed of a nitride semiconductor, an electron supply layer (104) that is formed on the electron transit layer (103), that is formed of a nitride semiconductor whose composition is different from the electron transit layer (103) and that has a recess (109) which reaches the electron transit layer (103) from a surface, a thermal oxide film (111) that is formed on the surface of the electron transit layer (103) exposed within the recess (109), a gate insulating film (110) that is embedded within the recess (109) so as to be in contact with the thermal oxide film (111), a gate electrode (108) that is formed on the gate insulating film (110) and that is opposite to the electron transit layer (103) across the thermal oxide film (111) and the gate insulating film (110), and a source electrode (106) and a drain electrode (107) that are provided on the electron supply layer (104) at an interval such that the gate electrode (108) intervenes therebetween.

A method of fabricating a microelectronic device, such as a high electron mobility transistors (HEMT), is disclosed. In some examples, the method comprises placing a masked semiconductor sample into a treatment chamber. An oxidizing gas is introduced into the treatment chamber and ionized by an inductively-coupled plasma (ICP)-only plasma source to form a first plasma that oxidizes an exposed region of the sample surface. The oxidizing gas is then evacuated from the treatment chamber, and a reducing gas is introduced into the treatment chamber. The reducing gas in the treatment chamber is ionized via the ICP-only plasma source to form a second plasma that reduces the exposed region of the sample surface. The sample may be heated to a temperature of at least about 100° C. (e.g., 200° C.), resulting in the etching/removal of a portion of the exposed region of the sample via chemical conversion and thermal desorption.

A dielectric structure for a nitride semiconductor device and a method of forming the same. A semiconductor device includes at least one semiconductor layer. The at least one semiconductor layer includes a gallium nitride semiconductor material. The semiconductor device also includes an oxidized layer disposed over the at least one semiconductor layer. The oxidized layer includes an oxidized form of the gallium nitride semiconductor of the at least one semiconductor layer. A silicon oxide layer is disposed over the oxidized layer. A gate is disposed over the silicon oxide layer.

A method for forming a group III-V semiconductor channel region in a transistor is provided herein. The method includes exposing a substrate including an oxide layer to a first plasma to treat the oxide layer, exposing the treated oxide layer to a second plasma to convert the oxide layer to an evaporable layer, evaporating the evaporable layer to expose a group III-V semiconductor material surface, and exposing the group III-V semiconductor material surface to an oxygen containing gas to oxidize the group III-V semiconductor material. The processes may be repeated until a recessed depth having a predetermined depth is formed. A group III-V semiconductor channel is then formed in the predetermined recessed depth. The control of the height of the group III-V semiconductor channel is improved.

The present disclosure provides a semiconductor structure in accordance with some embodiments. The semiconductor structure includes a semiconductor feature, a passivation layer that includes indium sulfide formed over a surface of the semiconductor feature. More particularly, the surface of the semiconductor feature comprises indium-based III-V compound semiconductor material.

A semiconductor device includes a first semiconductor layer made of a nitride semiconductor and formed on a substrate, a second semiconductor layer made of a material including InAlN and formed on the first semiconductor layer, an insulator layer formed by an oxidized surface part of the second semiconductor layer, a gate electrode formed on the insulator layer, and a source electrode and a drain electrode respectively formed on the first or second semiconductor layer.

A semiconductor device comprises: a nitride semiconductor layer; an oxide insulating film formed to contact the nitride semiconductor layer; and a gate electrode formed to contact the oxide insulating film and made of metal nitride in a crystal orientation including at least one of the (200) orientation and the (220) orientation.

A method for producing a semiconductor power device includes forming a gate trench from a surface of the semiconductor layer toward an inside thereof. A first insulation film is formed on the inner surface of the gate trench. The method also includes removing a part on a bottom surface of the gate trench in the first insulation film. A second insulation film having a dielectric constant higher than SiO2 is formed in such a way as to cover the bottom surface of the gate trench exposed by removing the first insulation film.

A second semiconductor layer is oxidized through a groove and a fourth semiconductor layer is oxidized, a first oxide layer is formed, and a second oxide layer is formed. By oxidizing the entire second semiconductor layer and the fourth semiconductor layer, the first oxide layer and the second oxide layer in an amorphous state are formed.

A nitride-based semiconductor device includes a first nitride-based semiconductor layer, a lattice layer, a third nitride-based semiconductor layer, a first source electrode and a second electrode, and a gate electrode. The second nitride-based semiconductor layer is disposed over the first nitride-based semiconductor layer. The lattice layer is disposed between the first and second nitride-based semiconductor layers and doped to the first conductivity type. The lattice layer comprises a plurality of first III-V layers and second III-V layers alternatively stacked. Each of the first III-V layers has a high resistivity region and a current aperture enclosed by the high resistivity region. The high resistivity region comprises more metal oxides than the current aperture so as to achieve a resistivity higher than that of the current aperture. At least two of the first III-V layers have the same group III element at different concentrations.