A semiconductor memory device includes a substrate with a cell array region and a connection region, an electrode structure including electrodes stacked on the substrate and having a staircase structure on the connection region, a vertical channel structure on the cell array region to penetrate the electrode structure and electrically connected to the substrate, a dummy structure on the connection region to penetrate the staircase structure, and a first sidewall oxide pattern interposed between the substrate and the dummy structure. The dummy structure includes an upper portion that is on the substrate, a middle portion that is in contact with the first sidewall oxide pattern, and a lower portion that is below the middle portion. With increasing vertical distance from the upper portion, a diameter of the middle portion decreases until it reaches its smallest value and then increases.

A method for manufacturing a semiconductor device includes providing a substrate including a first device region and a second device region spaced apart from each other, forming a first oxide layer on the first device region and the second device region, forming a second oxide layer below the first oxide layer, forming a mask layer on the first oxide layer on the first device region while exposing the first oxide layer on the second device region, removing the first and second oxide layers on the second device region using the mask layer as a mask, removing the mask layer, and forming a gate oxide layer on the second device region. The thus formed gate oxide layer structure has improved quality and reliability.

Embodiments relate to a semiconductor structure and a method for fabricating the same. The method includes: providing a substrate, where a plurality of first trench initial structures are formed on the substrate, and the first trench initial structures extend along a first direction; and sequentially performing a thermal oxidation process and an oxide etching process on trench walls of the first trench initial structures to form first trenches whose trench widths satisfy a first preset dimension. The semiconductor structure and the method for fabricating the same can precisely control a trench width dimension of a trench, to form an isolation structure having a precise dimension in the trench, thereby effectively reducing parasitic capacitance and improving production yield and electrical properties of the semiconductor structure.

A semiconductor device includes a substrate having at least a trench formed therein. A conductive material fills a lower portion of the trench. A barrier layer is between the conductive material and the substrate. An insulating layer is in the trench and completely covers the conductive material and the barrier layer, wherein a portion of the insulating layer covering the barrier layer has a bird's peak profile.

A method of forming a metal oxide semiconductor field effect transistor with improved gate-induced drain leakage performance, the method including providing a semiconductor substrate having a gate trench formed therein, performing an ion implantation process on upper portions of sidewalls of the gate trench to make the upper portions more susceptible to oxidation relative to non-implanted lower portions of the sidewalls, and performing an oxidation process on surfaces of the substrate, wherein the implanted upper portions of the sidewalls develop a thicker layer of oxidation relative to the non-implanted lower portions of the sidewalls.

A method of forming a metal oxide semiconductor field effect transistor with improved gate-induced drain leakage performance, the method including providing a semiconductor substrate having a gate trench formed therein, performing an ion implantation process on upper portions of sidewalls of the gate trench to make the upper portions more susceptible to oxidation relative to non-implanted lower portions of the sidewalls, and performing an oxidation process on surfaces of the substrate, wherein the implanted upper portions of the sidewalls develop a thicker layer of oxidation relative to the non-implanted lower portions of the sidewalls.

In an embodiment, a method includes: forming a fin extending from a substrate, the fin having a first width and a first height after the forming; forming a dummy gate stack over a channel region of the fin; growing an epitaxial source/drain in the fin adjacent the channel region; and after growing the epitaxial source/drain, replacing the dummy gate stack with a metal gate stack, the channel region of the fin having the first width and the first height before the replacing, the channel region of the fin having a second width and a second height after the replacing, the second width being less than the first width, the second height being less than the first height.

A memory device includes a substrate, a buried word line, a connecting structure, an air gap, and a first dielectric layer. The buried word line is disposed in the substrate. The connecting structure is disposed on the buried word line. The air gap is disposed on the buried word line and is adjacent to the connecting structure. The first dielectric layer is disposed on the connecting structure and the air gap, wherein the buried word line, the connecting structure, and the first dielectric layer are disposed in the first direction, which is substantially perpendicular to the top surface of the substrate.

Disclosed is a semiconductor device comprising a substrate including first and second PMOSFET regions, first and second active patterns on the first and second PMOSFET regions, first and second channel patterns on the first and second active patterns and each including semiconductor patterns, and first and second source/drain patterns connected to the first and second channel patterns. The first active pattern includes a first lower semiconductor layer, a first middle semiconductor layer, and a first upper semiconductor layer. Each of the first and second lower semiconductor layers includes silicon. The first middle semiconductor layer includes silicon-germanium. The first middle semiconductor layer has a width that decreases in a downward direction to a maximum value and then increases in the downward direction.

A second semiconductor layer is oxidized through a groove and a fourth semiconductor layer is oxidized, a first oxide layer is formed, and a second oxide layer is formed. By oxidizing the entire second semiconductor layer and the fourth semiconductor layer, the first oxide layer and the second oxide layer in an amorphous state are formed.