Embodiments of the present invention provide a method for removing a barrier layer of a metal interconnection on a wafer, which remove a single-layer metal ruthenium barrier layer. A method comprises: oxidizing step, is to oxidize the single-layer metal ruthenium barrier layer into a ruthenium oxide layer by electrochemical anodic oxidation process; oxide layer etching step, is to etch the ruthenium oxide layer with etching liquid to remove the ruthenium oxide layer. The present invention also provides a method for removing a barrier layer of a metal interconnection on a wafer, using in a structure of a process node of 10 nm and below, wherein the structure comprises a substrate, a dielectric layer, a barrier layer and a metal layer, the dielectric layer is deposited on the substrate and recessed areas are formed on the dielectric layer, the barrier layer is deposited on the dielectric layer, the metal layer is deposited on the barrier layer, wherein the metal layer is a copper layer, the barrier layer is a single-layer metal ruthenium layer, and the method comprises: thinning step, is to thin the metal layer; removing step, is to remove the metal layer; oxidizing step, is to oxidize the barrier layer, and the oxidizing step uses an electrochemical anodic oxidation process; oxide layer etching step, is to etch the oxidized barrier layer.

Provided are methods of making a long-term implantable electronic device, and related implantable devices, including by providing a substrate having a first encapsulation layer that covers at least a portion of the substrate, the first encapsulation layer having a receiving surface; providing one or more electronic devices on the first encapsulation layer receiving surface; and removing at least a portion of the substrate from the first encapsulation layer; thereby making the long-term implantable electronic device. Further desirable properties, including device lifetime increases during use in environments that are challenging for sensitive electronic device components, are achieved through the use of additional layers such as longevity-extending layers and/or ion-barrier layers in combination with an encapsulation layer.

Provided is a surface processing apparatus and a surface processing method for a SiC substrate using anodization. The surface processing apparatus for the SiC substrate includes a surface processing pad and a power supply device. The surface processing pad includes a grinding wheel layer. The grinding wheel layer is disposed facing a workpiece surface of the SiC substrate. The power supply device passes a pulsed current having a period greater than 0.01 seconds and less than or equal to 20 seconds for anodizing the workpiece surface to be processed by the grinding wheel layer through the SiC substrate as an anode in the presence of an electrolyte.

A surface processing method for a SiC substrate includes the following processes or steps: anodizing a workpiece surface of the SiC substrate by passing a current having a current density of 15 mA/cm.sup.2 or more through the SiC substrate as an anode in the presence of an electrolyte; disposing a grinding wheel layer of a surface processing pad to the workpiece surface and selectively removing, with the grinding wheel layer, an oxide formed on the workpiece surface through anodization; and performing, simultaneously or sequentially, the anodization of the workpiece surface and the selective removal of the oxide formed on the workpiece surface with the grinding wheel layer.

A method of manufacturing semiconductor chips having a side wall sealing is described. The method includes forming dicing trenches in a semiconductor wafer. The side walls of the dicing trenches are anodized to generate an anodic oxide layer at the side walls of the dicing trenches. Semiconductor chips are separated from the semiconductor wafer.

A method of fabricating a semiconductor structure that includes: forming a first metal layer over a wafer; forming a second metal layer over the first metal layer; forming a first porous structure in a first region of the second metal layer located above a circuit area of the wafer and a second porous structure in a second region of the second metal layer located above a dicing area of the wafer, wherein the first porous structure includes a first set of pores, and wherein the second porous structure includes a second set of pores; forming a metal-insulator-metal stack in the first set of pores of the first porous structure; and etching the second set of pores of the second porous structure to expose the dicing area of the silicon wafer.

A semiconductor device that includes a semiconductor substrate having a first main surface and a second main surface opposed to each other, and a porous metal oxide film on a side of the first main surface of the semiconductor substrate, the porous metal oxide film having a plurality of pores. The semiconductor substrate has a connection electrically connected to the porous metal oxide film, and the semiconductor substrate is configured to provide a power supply path from the second main surface to the connection on the first main surface.

Provided are methods of making a liquid and liquid vapor-proof material, and relates long-term implantable electronic devices. The method comprisies providing a first substrate having a first-side encapsulating layer supported by at least a portion of the first substrate; providing a material onto the first-side encapsulating layer; providing a second substrate having a second-side encapsulating layer supported by at least a portion of the second substrate; covering an exposed surface of the material provided onto the first-side encapsulation layer with the second-side encapsulating layer; wherein said encapsulating layers are substantially defect free so that liquid or liquid vapor is prevented from passing through each of the encapsulating layers; thereby making the liquid or liquid vapor-proof material.

An electrical device that includes: a metal barrier layer; an anodic porous oxide region on the metal barrier layer; a trench around the anodic porous oxide region reaching the metal barrier layer; a liner at least on a wall of the trench on a side of the anodic porous oxide region forming an electrical isolation barrier and having an opening onto the anodic porous oxide region; a hard mask arranged above the trenches and the liner having an opening onto the anodic porous oxide region. A corresponding manufacturing method is also disclosed.

A method for fabricating a metal oxide thin film transistor comprises selecting a substrate and fabricating a gate electrode thereon; growing a layer of dielectric or high permittivity dielectric on the substrate to serve as a gate dielectric layer; growing a first metal layer on the gate dielectric layer and a second metal layer on the first metal layer; fabricating a channel region at a middle position of the first metal layer and a passivation region at a middle position of the second metal layer; anodizing the metals of the passivation region and the channel region at atmospheric pressure and room temperature; fabricating a source and a drain; forming an active region comprising the source, the drain, and the channel region; depositing a silicon nitride layer on the active region; fabricating two electrode contact holes; depositing a metal aluminum film; and fabricating two metal contact electrodes by photolithography and etching.