Embodiments described herein provide for post deposition anneal of a substrate, having an amorphous carbon layer deposited thereon, to desirably reduce variations in local stresses thereacross. In one embodiment, a method of processing a substrate includes positioning a substrate, having an amorphous carbon layer deposited thereon, in a first processing volume, flowing an anneal gas into the first processing volume, heating the substrate to an anneal temperature of not more than about 450° C., and maintaining the substrate at the anneal temperature for about 30 seconds or more. Herein, the amorphous carbon layer was deposited on the substrate using a method which included positioning the substrate on a substrate support disposed in a second processing volume, flowing a processing gas into the second processing volume, applying pulsed DC power to a carbon target disposed in the second processing volume, forming a plasma of the processing gas, and depositing the amorphous carbon layer on the substrate.

To improve field-effect mobility and reliability of a transistor including an oxide semiconductor film. Provided is a semiconductor device including an oxide semiconductor film. The semiconductor device includes a first insulating film, the oxide semiconductor film over the first insulating film, a second insulating film and a third insulating film over the oxide semiconductor film, and a gate electrode over the second insulating film. The oxide semiconductor film includes a first oxide semiconductor film, a second oxide semiconductor film over the first oxide semiconductor film, and a third oxide semiconductor film over the second oxide semiconductor film. The first to third oxide semiconductor films contain the same element. The second oxide semiconductor film includes a region where the crystallinity is lower than the crystallinity of one or both of the first oxide semiconductor film and the third oxide semiconductor film.

A physical vapor deposition chamber comprising a tilting substrate support is described. Methods of processing a substrate are also provided comprising tilting at least one of the substrate and the target to improve the uniformity of the layer on the substrate from the center of the substrate to the edge of the substrate. Process controllers are also described which comprise one or more process configurations causing the physical deposition chamber to perform the operations of rotating a substrate support within the physical deposition chamber and tilting the substrate support at a plurality of angles with respect to a horizontal axis.

Provided is a ferroelectric field effect transistor (FeFET) which has a wide memory window even if the ferroelectric film thickness is 200 nm or less, and which has excellent data retention characteristics, pulse rewriting endurance and the like. An FeFET which has a structure wherein an insulating body (11) and a gate electrode conductor (4) are sequentially laminated in this order on a semiconductor base (10) that has a source region (12) and a drain region (13). The insulating body (11) is configured by laminating a first insulating body (1) and a second insulating body (2) in this order on the base (10), and the second insulating body (2) is mainly composed of an oxide of strontium, calcium, bismuth and tantalum.

After a sputtering gas is supplied to a deposition chamber, plasma including an ion of the sputtering gas is generated in the vicinity of a target. The ion of the sputtering gas is accelerated and collides with the target, so that flat-plate particles and atoms of the target are separated from the target. The flat-plate particles are deposited with a gap therebetween so that the flat plane faces a substrate. The atom and the aggregate of the atoms separated from the target enter the gap between the deposited flat-plate particles and grow in the plane direction of the substrate to fill the gap. A film is formed over the substrate. After the deposition, heat treatment is performed at high temperature in an oxygen atmosphere, which forms an oxide with a few oxygen vacancies and high crystallinity.

A sputtering method includes one or more sputtering processes. Each sputtering process includes in a first pre-sputtering phase, sputtering a target material on a baffle plate configured to shield a substrate; in a second pre-sputtering phase, sputtering a target material compound on the baffle plate; and in a main sputtering phase, sputtering the target material compound on the substrate. The first pre-sputtering phase is used to adjust a sputtering voltage for the main sputtering phase.

Provided are a deposition process monitoring system capable of detecting an internal state of a chamber in a deposition process, and a method of controlling the deposition process and a method of fabricating a semiconductor device using the system. The deposition process monitoring system includes a facility cover configured to define a space for a deposition process, a chamber located in the facility cover, covered with a translucent cover dome, and having a support on which a deposition target is placed, a plurality of lamps disposed in the facility cover, the lamps respectively disposed above and below the chamber, the lamps configured to supply radiant heat energy into the chamber during the deposition process, and a laser sensor disposed outside the chamber, the laser sensor configured to irradiate the cover dome with a laser beam and detect an intensity of the laser beam transmitted through the cover dome, wherein a state of by-products with which the cover dome is coated is determined based on the detected intensity of the laser beam.

A thin film deposition apparatus comprising: a laser pulse generator to generate a laser pulse; optical elements to optionally P-polarize and optionally rotate the laser pulse polarization with a polarization angle φ based on the cavity chamber and deposition material; focusing optics to focus the laser pulse; a source of deposition material having refractive index n.sub.2; said deposition material mounted within an evacuated chamber having a refractive index n.sub.1; a rotation and / or translation device to alter and / or direct said laser pulse onto said source of deposition material at an incidence angle θ to produce a plasma to be deposited on a substrate; wherein the polarization angle φ and incidence angle θ are defined by the area under the graphical representation of the ellipse of equation

[00001]$\frac{{\left(\theta -{\theta }_0\right)}^2}{a^2}+\frac{{\left(\phi -{\phi }_0\right)}^2}{b^2}=1$

where θ.sub.0=0.8× arctan (n.sub.2/n.sub.1), φ.sub.0=0, a=0.4× arctan (n.sub.2/n.sub.1) and b=0.5× arctan (n.sub.2/n.sub.1).

In accordance with an embodiment of the present invention, a method and semiconductor device is described, including forming a plurality of gaps of variable size between device features, each of the gaps including vertical sidewalls perpendicular to a substrate surface and a horizontal surface parallel to the substrate surface. Spacer material is directionally deposited concurrently on the horizontal surface in each gap and in a flat area using a total flow rate of gaseous precursors that minimizes gap-loading in a smallest gap compared to the flat area such that the spacer material is deposited on the substrate surface in each gap and in the flat area to a uniform thickness.

A semiconductor device with a small variation in characteristics is provided. The semiconductor device includes a first insulator; a second insulator having an opening over the first insulator; a third insulator that has a first depressed portion and is provided inside the opening; a first oxide that has a second depressed portion and is provided inside the first depressed portion; a second oxide provided inside the second depressed portion; a first conductor and a second conductor that are electrically connected to the second oxide and are apart from each other; a fourth insulator over the second oxide; and a third conductor including a region overlapping with the second oxide with the fourth insulator therebetween. The second oxide includes a first region, a second region, and a third region sandwiched between the first region and the second region in a top view. The first conductor includes a region overlapping with the first region and the second insulator. The second conductor includes a region overlapping with the second region and the second insulator. The third conductor includes a region overlapping with the third region.