Methods for the manufacture of stable strontium titanate nanocube sols are disclosed. The sols are useful in the manufacture of switchable layers suitable for RRAM applications and the switching performance is stable and reproducible. The RRAM layers comprise a mixture of strontium titanate nanocubes and surfactant.

An ink jet process is used to deposit a material layer to a desired thickness. Layout data is converted to per-cell grayscale values, each representing ink volume to be locally delivered. The grayscale values are used to generate a halftone pattern to deliver variable ink volume (and thickness) to the substrate. The halftoning provides for a relatively continuous layer (e.g., without unintended gaps or holes) while providing for variable volume and, thus, contributes to variable ink/material buildup to achieve desired thickness. The ink is jetted as liquid or aerosol that suspends material used to form the material layer, for example, an organic material used to form an encapsulation layer for a flat panel device. The deposited layer is then cured or otherwise finished to complete the process.

A lithographic printing plate precursor including an image recording layer containing an infrared absorber represented by Formula I, on a support, and a method of producing a lithographic printing plate and a lithographic printing method using the lithographic printing plate precursor. ##STR00001##

A manufacturing method of a multilayered board, includes: a dot pattern forming process that forms a dot pattern comprising at least one hemispherical micro-lens shape by repeating a process of forming one hemispherical micro-lens shape by jetting one droplet for forming the dot pattern in an inkjet manner; and a stack pattern forming process that forms a stack pattern having a thickness less than that of the micro-lens by jetting a droplet for forming the stack pattern on a predetermined area around the dot pattern in the inkjet manner.

A method of processing a semiconductor wafer includes: forming a first metal layer or metal layer stack on a backside of the semiconductor wafer; forming a plating preventative layer on the first metal layer or metal layer stack, the plating preventative layer being formed at least over a kerf region of the semiconductor wafer and such that part of the first metal layer or metal layer stack is uncovered by the plating preventative layer, wherein the kerf region defines an area for dividing the semiconductor wafer along the kerf region into individual semiconductor dies; and plating a second metal layer or metal layer stack on the part of the first metal layer or metal layer stack uncovered by the plating preventative layer, wherein the plating preventative layer prevents plating of the second metal layer or metal layer stack over the kerf region.

The present invention relates to a process for the production of structured, highly efficient solar cells and of photovoltaic elements which have regions of different doping. The invention likewise relates to the solar cells having increased efficiency produced in this way.

An integrated circuit (IC) with an impedance sensor fabricated on a surface of the substrate is disclosed. The impedance sensor includes a bottom conductive plate formed on the substrate. A sensing membrane is formed on the bottom conductive plate. A top conductive plate is formed on the sensing membrane, in which the top conductive plate is a fusion of conductive nanoparticles having a random three dimensional porosity that is permeable to a reagent.

Package-on-Package (PoP) structures and methods of forming the same are disclosed. In some embodiments, a method of forming a PoP structure may include: plating at least one through-assembly via (TAV) over a peripheral region of a conductive seed layer; forming a dam member over a central region of the conductive seed layer; and placing a die over the central region of the conductive seed layer. The dam member may be laterally separated from the die and disposed between the die and the at least one TAV. The method may further include encapsulating the die, the dam member, and the at least one TAV in a polymer material.

In various embodiments, a chip package is provided. The chip package may include a chip, a metal contact structure including a non-noble metal and electrically contacting the chip, a packaging material, and a protective layer including or essentially consisting of a portion formed at an interface between a portion of the metal contact structure and the packaging material, wherein the protective layer may include a noble metal, wherein the portion of the protective layer may include a plurality of regions free from the noble metal, and wherein the regions free from the noble metal may provide an interface between the packaging material and the non-noble metal of the metal contact structure.

An integrated circuit assembly including an integrated circuit formed on one side of a substrate and a thermal spreading layer composed of a silver ink directly printed on an opposite side of the substrate from the integrated circuit, where the thermal spreading layer removes heat generated by the integrated circuit. The assembly also includes a heat sink thermally attached to the thermal spreading layer opposite to the substrate, where the heat sink is attached to the thermal spreading layer by printing the same material on the heat sink as the thermal spreading layer and pressing the spreading layer to the heat sink.