Generally, the present disclosure provides example embodiments relating to formation of a gate structure of a device, such as in a replacement gate process, and the device formed thereby. In an example method, a gate dielectric layer is formed over an active area on a substrate. A dummy layer that contains a passivating species (such as fluorine) is formed over the gate dielectric layer. A thermal process is performed to drive the passivating species from the dummy layer into the gate dielectric layer. The dummy layer is removed. A metal gate electrode is formed over the gate dielectric layer. The gate dielectric layer includes the passivating species before the metal gate electrode is formed.

Embodiments described herein relate to a method for patterning a doping layer, such as a lanthanum containing layer, used to dope a high-k dielectric layer in a gate stack of a FinFET device for threshold voltage tuning. A blocking layer may be formed between the doping layer and a hard mask layer used to pattern the doping layer. In an embodiment, the blocking layer may include or be aluminum oxide (AlO.sub.x). The blocking layer can prevent elements from the hard mask layer from diffusing into the doping layer, and thus, can improve reliability of the devices formed. The blocking layer can also improve a patterning process by reducing patterning induced defects.

A semiconductor device includes a semiconductor feature, a low-k dielectric feature that is formed on the semiconductor feature, and a Si-containing layer that contains elements of silicon and that covers over the low-k dielectric feature. The Si-containing layer can prevent the low-k dielectric feature from being damaged in etch and/or annealing processes for manufacturing the semiconductor device.

The present disclosure appropriately shortens a processing step for processing a substrate in which a silicon layer and a silicon germanium layer are alternatively laminated. The present disclosure provides a substrate processing method of processing the substrate in which the silicon layer and the silicon germanium layer are alternatively laminated, which includes forming an oxide film by selectively modifying a surface layer of an exposed surface of the silicon germanium layer by using a processing gas including fluorine and oxygen and converted into plasma.

A topological material includes a lattice crystalline structure; and a material defect in the lattice crystalline structure that is treatable by hydrogen passivation that chemically mitigates an electronic charge associated with the material defect. The lattice crystalline structure includes dangling bonds in an atomic arrangement of the material defect of the lattice crystalline structure, and the hydrogen passivation may apply hydrogen to chemically passivate the dangling bonds of the material defect. The hydrogen passivation may be achieved by diffusing hydrogen into common materials of the lattice crystalline structure. The hydrogen passivation may chemically and/or electrostatically neutralize an electronic activity associated with the material defect.

Films are modified to include deuterium in an inductive high density plasma chamber. Chamber hardware designs enable tunability of the deuterium concentration uniformity in the film across a substrate. Manufacturing of solid state electronic devices include integrated process flows to modify a film that is substantially free of hydrogen and deuterium to include deuterium.

In a variety of processes for forming electronic devices that use spin-on dielectric materials, properties of the spin-on dielectric materials can be enhanced by curing these materials using plasma doping. For example, hardness and Young's modulus can be increased for the cured material. Other properties may be enhanced. The plasma doping to cure the spin-on dielectric materials uses a mechanism that is a combination of plasma ion implant and high energy radiation associated with the species ionized. In addition, physical properties of the spin-on dielectric materials can be modified along a length of the spin-on dielectric materials by selection of an implant energy and dopant dose for the particular dopant used, corresponding to a selection variation with respect to length.

The present disclosure provides a processing method for semiconductor surface defects and a preparation method for semiconductor devices. The processing method for semiconductor surface defects includes: placing a semiconductor device in a plasma processing device, the semiconductor device comprising a semiconductor substrate and deposition layers formed on the surface of the semiconductor substrate, bubbles being formed in the deposition layers; and plasma bombarding the surface of the deposition layer to break the bubbles, so that the surface of the deposition layer is flat.

A ferroelectric semiconductor device and method are described herein. The method includes performing a diffusion anneal process to drive elements of a dopant film through an amorphous silicon layer and into a gate dielectric layer over a fin to form a doped gate dielectric layer with a gradient depth profile of dopant concentrations. The doped gate dielectric layer is crystallized during a post-cap anneal process to form a gradient depth profile of ferroelectric properties within the crystallized gate dielectric layer. A metal gate electrode is formed over the crystallized gate dielectric layer to obtain a ferroelectric transistor with multi-ferroelectric properties between the gate electrode and the channel. The ferroelectric transistor may be used in deep neural network (DNN) applications.

A method may include providing a substrate having, on a first surface of the substrate, a low dielectric constant layer characterized by a layer thickness. The method may include heating the substrate to a substrate temperature in a range of 200° C. to 550° C.; and directing an ion implant treatment to the low dielectric constant layer, while the substrate temperature is in the range of 200° C. to 550° C. As such, the ion implant treatment may include implanting a low weight ion species, at an ion energy generating an implant depth equal to 40% to 175% of the layer thickness.