In an embodiment, a device includes: a gate structure over a substrate; a gate spacer adjacent the gate structure; a source/drain region adjacent the gate spacer; a first inter-layer dielectric (ILD) on the source/drain region, the first ILD having a first concentration of an impurity; and a second ILD on the first ILD, the second ILD having a second concentration of the impurity, the second concentration being less than the first concentration, top surfaces of the second ILD, the gate spacer, and the gate structure being coplanar; and a source/drain contact extending through the second ILD and the first ILD, the source/drain contact coupled to the source/drain region.

Embodiments of the present disclosure describe techniques for oxidizing plasma post-treatment for reducing photolithography poisoning. In one embodiment, an apparatus includes a dielectric layer with a plurality of routing features; and an etch stop layer, having a first interface region coupled with the dielectric layer and a second interface region disposed opposite to the first interface region. The first interface region has a peak silicon oxide (SiO.sub.2) concentration level evenly distributed across the first interface region, and the second interface region has substantially zero silicon oxide (SiO.sub.2) concentration level. Other embodiments may be described and/or claimed.

The present invention provides a method of manufacturing a bonded wafer, including performing RTA under an atmosphere containing hydrogen on a bonded wafer after separating the bond wafer constituting the bonded wafer, and subsequently performing a sacrificial oxidation process to reduce the thickness of the thin film, wherein the RTA is performed under conditions of a retention start temperature of more than 1150° C. and a retention end temperature of 1150° C. or less. The invention can inhibit the BMD density from increasing and sufficiently flatten the surface of a thin film when the thin film of the bonded wafer is flattened and thinned by the combination of the RTA and sacrificial oxidation processes.

Provided is a memory device including a substrate, a plurality of word-line structures, a plurality of cap structures, and a plurality of air gaps. The word-line structures are disposed on the substrate. The cap structures are respectively disposed on the word-line structures. A material of the cap structures includes a nitride. The nitride has a nitrogen concentration decreasing along a direction near to a corresponding word-line structure toward far away from the corresponding word-line structure. The air gaps are respectively disposed between the word-line structures. The air gaps are in direct contact with the word-line structures. A method of forming a memory device is also provided.

In one aspect of the invention, a method for fabricating an advanced metal conductor structure includes a conductive line pattern including a set of conductive line trenches in a dielectric layer. Each conductive line trench of the conductive line pattern has parallel vertical sidewalls and a horizontal bottom. A surface treatment of the dielectric layer is performed. The surface treatment produces an element enriched surface layer in which a concentration of a selected element in a surface portion of the parallel sidewalls and horizontal bottoms of the conductive line trenches is increased. A first metal layer is deposited on the element enriched surface layer. A first thermal anneal is performed which simultaneously reflows the first metal layer to fill a first portion of the conductive line trenches and causes a chemical change at interfaces of the first metal layer and the element enriched surface layer creating a liner which is an alloy of the first metal and selected element. A second metal layer is deposited. A second thermal anneal is performed which reflows the second metal layer to fill a remaining portion of the conductive line trenches. Another aspect of the invention is a device formed by the process.

A method for fabricating a semiconductor device includes: forming a silicon nitride film having a refractive index equal to or larger than 2.2 on a nitride semiconductor layer; and introducing at least one of elements that are oxygen, nitrogen, fluorine, phosphorus, sulfur and selenium into the silicon nitride film, the silicon nitride film including the at least one of elements remaining on the nitride semiconductor layer. The at least one of elements is introduced by a process of exposing the silicon nitride film to plasma including the at least one of elements, a process of ion-implanting the at least one of elements into the silicon nitride film, or a process of thermally diffusing the at least one of elements into the silicon nitride film. The silicon nitride film is formed in contact with a surface of the nitride semiconductor layer.

A semiconductor device structure is provided. The semiconductor device includes a first nanowire structure over a second nanowire structure, a gate stack wrapping around the first nanowire structure and the second nanowire structure, a source/drain feature adjoining the first nanowire structure and the second nanowire structure, a gate spacer layer over the first nanowire structure and between the gate stack and the source/drain feature, and an inner spacer layer between the first nanowire structure and the second nanowire structure and between the gate stack and the source/drain feature. The gate spacer layer has a first carbon concentration, the inner spacer has a second carbon concentration, and the second carbon concentration is lower than the first carbon concentration.

A semiconductor device having favorable electrical characteristics is provided. The semiconductor device includes a first oxide; a first conductor and a second conductor over the first oxide; a first insulator over the first conductor; a second insulator over the second conductor; a third insulator over the first insulator and the second insulator; a second oxide positioned over the first oxide and between the first conductor and the second conductor; a fourth insulator over the second oxide; a third conductor over the fourth insulator; a fifth insulator in contact with a top surface of the third insulator, a top surface of the second oxide, a top surface of the fourth insulator, and a top surface of the third conductor; a fourth conductor embedded in an opening formed in the first insulator, the third insulator, and the fifth insulator and in contact with the first conductor; and a fifth conductor embedded in an opening formed in the second insulator, the third insulator, and the fifth insulator and in contact with the second conductor. The third insulator includes, in the vicinity of an interface with the fourth conductor and in the vicinity of an interface with the fifth conductor, a region having a higher nitrogen concentration than a different region of the third insulator.

A method of fabricating an integrated circuit (IC) structure, includes forming a gate trench that exposes a portion of each of a plurality of fins and forming a threshold voltage (Vt) tuning dielectric layer in the gate trench over the plurality of fins. Properties of the Vt tuning dielectric layer are adjusted during the forming to achieve a different Vt for each of the plurality of fins. The method also includes forming a glue metal layer over the Vt tuning dielectric layer; and forming a fill metal layer over the glue metal layer. The fill metal layer has a substantially uniform thickness over top surfaces of the plurality of fins.

Aspects of the present disclosure are related to a semiconductor device that includes a crystalline substrate having a first surface and a second surface vertically opposite each other and an insulating layer disposed on the first surface of the crystalline substrate. The device may also include an etch stop layer interposed between and contacting the crystalline substrate and the insulating layer and a conductive through via structure penetrating the crystalline substrate and the insulating layer. The device may also include an insulating separation layer disposed horizontally adjacent to the conductive through via structure, and having an inner wall and an outer wall. The insulating separation layer may include a first portion disposed between the conductive through via structure and the crystalline substrate, and a second portion disposed between the conductive through via structure and the etch stop layer.