In a method of manufacturing a semiconductor device, a first fin structure, a second fin structure, a first wall fin structure and a second wall fin structure are formed over a substrate. The first and second fin structures are disposed between the first and second wall fin structures, and lower portions of the first and second fin structures and the first and second wall fin structures are embedded in the isolation insulating layer and upper portions thereof are exposed from the isolation insulating layer. A sidewall spacer layer is formed on sidewalls of the first and second fin structures. Source/drain regions of the first and second fin structures are recessed. An epitaxial source/drain structure is formed over the recessed first and second fin structures. A width W1 of the first and second fin structures is smaller than a thickness W2 of the sidewall spacer layer.

A composition for use in selective modification of a base material surface includes a polymer having, at an end of a main chain or a side chain thereof, a group including a first functional group capable of forming a bond with a metal, and a solvent.

A system for processing a semiconductor wafer is provided. The system includes a processing tool. The system also includes gas handling housing having a gas inlet and a gas outlet. The system further includes an exhaust conduit fluidly communicating with the processing tool and the gas inlet of the gas handling housing. In addition, the system includes at least one first filtering assembly and at least one second filtering assembly. The first filtering assembly and the second filtering assembly are positioned in the gas handling housing and arranged in a series along a flowing path that extends from the gas inlet to the gas outlet of the gas handling housing. Each of the first filtering assembly and the second filtering assembly comprises a plurality of wire meshes stacked on top of another.

A method of manufacturing a semiconductor device includes forming a first nitride semiconductor layer containing Ga on a substrate; forming a first layer on the first nitride semiconductor layer; forming a second layer on the first layer; forming an opening in which the first nitride semiconductor layer is exposed in the second layer and the first layer; forming a second nitride semiconductor layer of a first conductivity type on a surface, exposed in the opening, of the first nitride semiconductor layer; removing the second layer using an acidic solution; and after removing the second layer, forming an electrode on the second nitride semiconductor layer. A first etching rate of the first layer for the acidic solution is lower than a second etching rate of the second layer for the acidic solution.

In one embodiment, a particle with a first particle thickness may be formed on a film with a first thickness, followed by a plasma treatment. The first particle thickness may be reduced to a second particle thickness below an allowable limit and the first film thickness may be reduced to a second film thickness by the plasma treatment. In another embodiment, a particle with a first particle thickness may be formed on a first film with a first film thickness, followed by a plasma treatment. The first particle thickness may be reduced to a second particle thickness below an allowable limit and the first film thickness may be reduced to a second film thickness by the plasma treatment. After the plasma treatment, a second film with a third film thickness may be deposited on the first film and the particle may be buried in the second film.

The present disclosure includes apparatuses and methods related to freezing a sacrificial material in forming a semiconductor. In an example, a method may include solidifying, via freezing, a sacrificial material in an opening of a structure, wherein the sacrificial material has a freezing point below a boiling point of a solvent used in a wet clean operation and removing the sacrificial material via sublimation by exposing the sacrificial material to a particular temperature range.

The invention provides a method for forming a semiconductor structure. The method includes providing a substrate, forming a gate structure on the substrate, respectively forming an epitaxial layer on both sides of the gate structure, and performing a pre-amorphization doping step on the substrate. After the pre-amorphization doping step, a defect is generated in the epitaxial layer, an outer spacer is formed beside the gate structure, and a chemical cleaning step is performed to remove a part of the epitaxial layer, and the defect in the epitaxial layer is removed.

A method for manufacturing a semiconductor memory includes: providing a portion to be processed, and performing a preset process step on the portion to be processed at least after a minimum waiting time; before performing the preset process step, performing a thermal oxidation process on the portion to be processed; and before performing the preset process step, performing a cleaning process, the cleaning process being used to remove oxides from the surface of the portion to be processed, the oxides being wholly or partly generated by the thermal oxidation process.

A method of producing a semiconductor device including: providing a temporary fixing laminate having a supporting substrate; machining a semiconductor member that is temporarily fixed to the supporting substrate; and separating the semiconductor member from the supporting substrate by irradiating the temporary fixing laminate with light from a side of a rear surface of the supporting substrate. A plurality of the irradiation target regions set at the rear surface are sequentially irradiated with light, and each of the irradiation target regions includes a part of the rear surface. The irradiation target regions adjacent to each other partially overlap with each other as viewed from a direction perpendicular to the rear surface, and a region in which the plurality of the irradiation target regions are combined includes the entire rear surface.

In an example, a wet cleaning process is performed to clean a structure having features and openings between the features while preventing drying of the structure. After performing the wet cleaning process, a polymer solution is deposited in the openings while continuing to prevent any drying of the structure. A sacrificial polymer material is formed in the openings from the polymer solution. The structure may be used in semiconductor devices, such as integrated circuits, memory devices, MEMS, among others.