A method includes removing a first dummy gate structure to form a recess around a first nanostructure and a second nanostructure; depositing a sacrificial layer in the recess with a flowable chemical vapor deposition (CVD); and patterning the sacrificial layer to leave a portion of the sacrificial layer between the first nanostructure and the second nanostructure. The method further include depositing a first work function metal in first recess; removing the first work function metal and the portion of the sacrificial layer from the recess; depositing a second work function metal in the recess, wherein the second work function metal is of an opposite type than the first work function metal; and depositing a fill metal over the second work function metal in the recess.

A method for shallow trench isolation structures in a semiconductor device and a semiconductor device including the shallow trench isolation structures are disclosed. In an embodiment, the method may include forming a trench in a substrate; depositing a first dielectric liner in the trench; depositing a first shallow trench isolation (STI) material over the first dielectric liner, the first STI material being deposited as a conformal layer; etching the first STI material; depositing a second STI material over the first STI material, the second STI material being deposited as a flowable material; and planarizing the second STI material such that top surfaces of the second STI material are co-planar with top surfaces of the substrate.

A method for filling a gap feature on a substrate surface is disclosed. The method may include: providing a substrate comprising a non-planar surface including one or more gap features; depositing a metal oxide film over a surface of the one or more gap features by a cyclical deposition process; contacting the metal oxide with an organic ligand vapor; and converting at least a portion of the metal oxide film to a porous material thereby filling the one or more gap features. Semiconductor structures including a metal-organic framework material formed by the methods of the disclosure are also disclosed.

A pattern formation method includes forming an organic film on a substrate, processing the organic film to form an organic film pattern, exposing the organic film pattern to an organic gas, and exposing the organic film pattern to a metal-containing gas, and after (i) exposing the organic film pattern to the organic gas and (ii) exposing the organic film pattern to the metal-containing gas, treating the organic film pattern with an oxidizing agent.

Methods and apparatuses for depositing material into high aspect ratio features are described herein. Methods involve depositing an oxide material using a hydrogen-containing oxidizing chemistry. Methods may also involve thermally treating deposited oxide material in the presence of hydrogen to remove seams within the deposited oxide material.

Methods for filling the gap of a semiconductor feature comprising exposure of a substrate surface to a precursor and reactant and an anneal environment to decrease the wet etch rate ratio of the deposited film and fill the gap.

Methods for seam-less gapfill comprising forming a flowable film by exposing a substrate surface to a silicon-containing precursor and a co-reactant are described. The silicon-containing precursor has at least one akenyl or alkynyl group. The flowable film can be cured by any suitable curing process to form a seam-less gapfill.

Pedestal assemblies, purge rings for pedestal assemblies, and processing methods for increasing residence time of an edge purge gas in heated pedestal assemblies are described. Purge rings have an inner diameter face and an outer diameter face defining a thickness of the purge ring, a top surface and a bottom surface defining a height of the purge ring, and a thermal expansion feature. Purge rings comprise a plurality of apertures extending through the thickness and aligned circumferentially with a plurality of circumferentially spaced purge outlets in a substrate support.

A semiconductor wafer to be treated is heated at a first preheating temperature ranging from 100 to 200° C. while a pressure in a chamber housing the semiconductor wafer is reduced to a pressure lower than an atmospheric pressure. After the semiconductor wafer is preheated to increase the temperature into a second preheating temperature ranging from 500 to 700° C. while the pressure in the chamber is restored to a pressure higher than the reduced pressure, a flash lamp emits a flashlight to a surface of the semiconductor wafer. Heating the semiconductor wafer at the first preheating temperature that is a relatively low temperature enables, for example, the moisture absorbed on the surface of the semiconductor wafer in trace amounts to be desorbed from the surface, and also enables the flash heating treatment to be performed with oxygen derived from such absorption removed as much as possible.

Embodiments of the present disclosure provide an apparatus and methods for forming stair-like structures with accurate profiles and dimension control for manufacturing three dimensional (3D) stacked memory cell semiconductor devices. In one embodiment, a memory cell device includes a film stack comprising alternating pairs of dielectric layers and conductive structures horizontally formed on a substrate, and an opening formed in the film stack, wherein the opening is filled with a metal dielectric layer, a multi-layer structure and a center filling layer, wherein the metal dielectric layer in the opening is interfaced with the conductive structure.