Patent classifications
H01L21/02337
Method for manufacturing semiconductor structure with enlarged volumes of source-drain regions
A method for smoothing a surface of a semiconductor portion is disclosed. In the method, an intentional oxide layer is formed on the surface of the semiconductor portion, a treated layer is formed in the semiconductor portion and inwardly of the intentional oxide layer, and then, the intentional oxide layer and the treated layer are removed to obtain a smoothed surface. The method may also be used for widening a recess in a manufacturing process for a semiconductor structure.
Flowable Chemical Vapor Deposition (FcvD) Using Multi-Step Anneal Treatment and Devices Thereof
FCVD using multi-step anneal treatment and devices thereof are disclosed. In an embodiment, a method includes depositing a flowable dielectric film on a substrate. The flowable dielectric film is deposited between a first semiconductor fin and a second semiconductor fin. The method further includes annealing the flowable dielectric film at a first anneal temperature for at least 5 hours to form a first dielectric film, annealing the first dielectric film at a second anneal temperature higher than the first anneal temperature to form a second dielectric film, annealing the second dielectric film at a third anneal temperature higher than the first anneal temperature to form an insulating layer, applying a planarization process to the insulating layer, and etching the insulating layer to STI regions on the substrate.
Varying temperature anneal for film and structures formed thereby
Semiconductor device structures having dielectric features and methods of forming dielectric features are described herein. In some examples, the dielectric features are formed by an ALD process followed by a varying temperature anneal process. The dielectric features can have high density, low carbon concentration, and lower k-value. The dielectric features formed according to the present disclosure has improved resistance against etching chemistry, plasma damage, and physical bombardment in subsequent processes while maintaining a lower k-value for target capacitance efficiency.
Semiconductor-on-insulator (SOI) substrate and method for forming
Various embodiments of the present application are directed towards a semiconductor-on-insulator (SOI) substrate. The SOI substrate includes a handle substrate; a device layer overlying the handle substrate; and an insulator layer separating the handle substrate from the device layer. The insulator layer meets the device layer at a first interface and meets the handle substrate at a second interface. The insulator layer comprises a getter material having a getter concentration profile. The handle substrate contains getter material and has a handle getter concentration profile. The handle getter concentration profile has a peak at the second interface and a gradual decline beneath the second interface until reaching a handle getter concentration.
METHOD, SEMICONDUCTOR STRUCTURE, AND VACUUM PROCESSING SYSTEM
This disclosure relates to a method (100) for passivating a semiconductor structure, comprising a semiconductor layer and an oxide layer on the semiconductor layer; a semiconductor structure; and a vacuum processing system. The method (100) comprises providing the semiconductor structure (110) in a vacuum chamber (310) and, while keeping the semiconductor structure in the vacuum chamber (120) throughout a refinement period with a duration of at least 25 s refining the oxide layer (130) by maintaining temperature (131) of the semiconductor structure within a refinement temperature range extending from 20° C., to 800° C., and maintaining total pressure (132) in the vacuum chamber below a maximum total pressure, of 1×10.sup.−3 mbar.
INTEGRATED CIRCUIT WITH GETTER LAYER FOR HYDROGEN ENTRAPMENT
An integrated circuit (IC) substrate manufacturing process provides time-dependent device characteristic variation due to hydrogen absorption by including one or more gettering layers near the devices that would otherwise absorb hydrogen and exhibit the variation as the hydrogen migrates in the devices. The method includes forming or mounting the devices on a top surface of the semiconductor wafer in die areas of the substrate, forming semiconductor structures in the semiconductor die areas, forming a getter layer above or adjacent to the devices in the die areas, and processing the wafer with one or more processes exposing the wafer to vapor having a hydrogen content, whereby an amount of hydrogen absorbed by the devices is reduced by presence of the getter layer. The method produces wafers including semiconductor dies with reduced hydrogen absorption by the devices and packaged ICs including the dies.
SEMICONDUCTOR DEVICE, AND METHOD FOR PROTECTING LOW-K DIELECTRIC FEATURE OF SEMICONDUCTOR DEVICE
A semiconductor device includes a semiconductor feature, a low-k dielectric feature that is formed on the semiconductor feature, and a Si-containing layer that contains elements of silicon and that covers over the low-k dielectric feature. The Si-containing layer can prevent the low-k dielectric feature from being damaged in etch and/or annealing processes for manufacturing the semiconductor device.
Methods, systems, and apparatus for processing substrates using one or more amorphous carbon hardmask layers
Aspects generally relate to methods, systems, and apparatus for processing substrates using one or more amorphous carbon hardmask layers. In one aspect, film stress is altered while facilitating enhanced etch selectivity. In one implementation, a method of processing a substrate includes depositing one or more amorphous carbon hardmask layers onto the substrate, and conducting a rapid thermal anneal operation on the substrate after depositing the one or more amorphous carbon hardmask layers. The rapid thermal anneal operation lasts for an anneal time that is 60 seconds or less. The rapid thermal anneal operation includes heating the substrate to an anneal temperature that is within a range of 600 degrees Celsius to 1,000 degrees Celsius. The method includes etching the substrate after conducting the rapid thermal anneal operation.
THIN-FILM DEPOSITION METHOD AND SEMICONDUCTOR DEVICE
The present application discloses a thin-film deposition method and a semiconductor device. The thin-film deposition method in the present application includes: providing a substrate; performing thin-film deposition on the substrate by using a thin-film deposition technology to form a first deposited layer; introducing a purge gas to perform impurity purge treatment on the first deposited layer to form a purified deposited layer; and forming a thin-film layer by the purified deposited layer. In the thin-film deposition method of the present application, the thin-film deposition technology is adopted to form the deposited layer, and impurity purge treatment is performed on the deposited layer.
METHOD OF PROCESSING SUBSTRATE, METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE, SUBSTRATE PROCESSING APPARATUS, AND RECORDING MEDIUM
A method for forming an oligomer-containing layer on a substrate and in a concave portion formed on the substrate by performing a cycle a predetermined number of times under a first temperature, the cycle including supplying a precursor gas to the substrate, and supplying first and second nitrogen- and hydrogen-containing gases to the substrate, so an oligomer including an element in at least one selected from the group of the precursor gas, and the first and second nitrogen-hydrogen-containing gasses, flowed in the concave portion, and (b) forming a film to fill the inside of the concave portion by post-treating the substrate, which has the oligomer-containing layer formed on the surface of the substrate and in the concave portion, under a second temperature not less than the first temperature, so that the oligomer-containing layer formed in the concave portion is modified to form the film.