Embodiments described herein relate generally to methods for forming a conductive feature in a dielectric layer in semiconductor processing and structures formed thereby. In some embodiments, a structure includes a dielectric layer over a substrate, a surface modification layer, and a conductive feature. The dielectric layer has a sidewall. The surface modification layer is along the sidewall, and the surface modification layer includes phosphorous and carbon. The conductive feature is along the surface modification layer.

A method for manufacturing a semiconductor device including: a process of applying a sealing composition for a semiconductor to a semiconductor substrate, to form a sealing layer for a semiconductor on at least the bottom face and the side face of a recess portion of an interlayer insulating layer, the sealing composition including a polymer having a cationic functional group and a weight average molecular weight of from 2,000 to 1,000,000, each of the content of sodium and the content of potassium in the sealing composition being 10 ppb by mass or less on an elemental basis; and a process of subjecting a surface of the semiconductor substrate at a side at which the sealing layer has been formed to heat treatment of from 200° C. to 425° C., to remove at least a part of the sealing layer.

An apparatus for cleaning a wafer includes a wafer station configured to hold the wafer, and a first and a second dispensing system. The first dispensing system includes a first swivel arm, and a first nozzle on the first swivel arm, wherein the first swivel arm is configured to move the first nozzle over and aside of the wafer. The first dispensing system includes first storage tank connected to the first nozzle, with the first nozzle configured to dispense a solution in the first storage tank. The second dispensing system includes a second swivel arm, and a second nozzle on the second swivel arm, wherein the second swivel arm is configured to move the second nozzle over and aside of the wafer. The second dispensing system includes a second storage tank connected to the second nozzle, with the second nozzle configured to dispense a solution in the second storage tank.

Embodiments of three-dimensional (3D) memory devices with an enlarged joint critical dimension and methods for forming the same are disclosed. In an example, a 3D memory device is disclosed. The 3D memory device includes a substrate, a memory stack having a plurality of interleaved conductor layers and dielectric layers on the substrate, and a memory string extending vertically through the first memory stack and having a memory film along a sidewall of the memory string. The memory film includes a discontinuous blocking layer interposed by the dielectric layers.

The present disclosure provides a thin film transistor, a method for preparing the same, a display substrate, and a display device. The thin film transistor includes a gate electrode, a semiconductor layer, and a gate insulation layer arranged between the gate electrode and the semiconductor layer, and the gate insulation layer includes a metal oxide layer and a modified layer formed through self-assembling on a side of the metal oxide layer away from the gate electrode and.

Disclosed herein are techniques for providing isolation in integrated circuit (IC) devices, as well as IC devices and computing systems that utilize such techniques. In some embodiments, a protective layer may be disposed on a structure in an IC device, prior to deposition of additional dielectric material, and the resulting assembly may be treated to form a dielectric layer around the structure.

A method of forming a semiconductor device includes forming a sacrificial gate structure over a substrate, depositing a spacer layer on the sacrificial gate structure in a conformal manner, performing a multi-step oxidation process to the spacer layer, etching the spacer layer to form gate sidewall spacers on opposite sidewalls of the sacrificial gate structure, removing the sacrificial gate structure to form a trench between the gate sidewalls spacers, and forming a metal gate structure in the trench.

A method used in forming integrated circuitry comprises forming a stack comprising vertically-alternating first tiers and second tiers. A stair-step structure is formed into the stack. A first liquid is applied onto the stair-step structure. The first liquid comprises insulative physical objects that individually have at least one of a maximum submicron dimension or a minimum submicron dimension. The first liquid is removed to leave the insulative physical objects touching one another and to have void-spaces among the touching insulative physical objects. A second liquid that is different from the first liquid is applied into the void-spaces. The second liquid is changed into a solid insulative material in the void-spaces. Other embodiments, including structure, are disclosed.

A substrate processing method includes a first processing step of processing a substrate using phosphoric acid set to a first temperature in a processing tank, and a second processing step of processing the substrate using phosphoric acid set to a second temperature in the processing tank.

Disclosed is a method of forming a semiconductor device. The method includes providing a precursor having a substrate and protrusions over the substrate. The protrusions are interposed by trenches. The method further includes depositing a first dielectric layer over the protrusions and filling the trenches. The first dielectric layer has a first hardness. The method further includes treating the first dielectric layer with an oxidizer. The method further includes performing a chemical mechanical planarization (CMP) process to the first dielectric layer.