In one embodiment, a semiconductor device includes a stacked film alternately including a plurality of electrode layers and a plurality of insulating layers. The device further includes a first insulator, a charge storage layer, a second insulator and a first semiconductor layer that are disposed in order in the stacked film. The device further includes a plurality of first films disposed between the first insulator and the plurality of insulating layers. Furthermore, at least one of the first films includes a second semiconductor layer.

A method can include ion implanting with the gate mask to form first halo regions and ion implanting with the gate mask and first spacers as a mask to form second halo regions. The gate mask and first spacers can be removed, and an epitaxial layer formed. A dummy gate mask can be formed. Ion implanting with the dummy gate mask can from source-drain extensions. Second spacers can be formed on sides of the dummy gate mask. Ion implanting with the dummy gate mask and second spacers as a mask can form source and drain regions. A surface dielectric layer can be formed and planarized to expose a top of the dummy gate. The dummy gate can be removed to form gate openings between the second spacers. A hi-K dielectric layer and at least two gate metal layers within the gate opening. Related devices are also disclosed.

A transistor includes a multilayer film in which an oxide semiconductor film and an oxide film are stacked, a gate electrode, and a gate insulating film. The multilayer film overlaps with the gate electrode with the gate insulating film interposed therebetween. The multilayer film has a shape having a first angle between a bottom surface of the oxide semiconductor film and a side surface of the oxide semiconductor film and a second angle between a bottom surface of the oxide film and a side surface of the oxide film. The first angle is acute and smaller than the second angle. Further, a semiconductor device including such a transistor is manufactured.

A display apparatus may include a base substrate including a first portion and a second portion smaller than the first portion, a plurality of pixels disposed on the first portion, a protection substrate disposed below the base substrate, and a groove disposed in a portion of the protection substrate and overlapped with the second portion. The groove may include a first region extending in a first direction, and a second region and a third region, which are arranged along the first direction, wherein the first region is interposed between the second region and the third region. The first and second portions may be arranged in a second direction crossing the first direction, and a width of each of the second and third regions may be larger than a first width of the first region, when measured in the second direction.

Method for manufacturing a semiconductor device includes: forming a first area and a second area of a peripheral area on a substrate; forming a first lamination structure in the first area, and forming a second lamination structure in an array area and the second area; performing thermal treatment on the substrate so that atoms in a work function layer are diffused into a second dielectric layer, and an interface interaction occurs between the second dielectric layer and a first dielectric layer; removing the first lamination structure to the second dielectric layer, and removing the second lamination structure to the second dielectric layer; forming a fourth barrier layer and a second conductive layer, a content ratio of metallic element to non-metallic element in a first barrier layer being less than a content ratio of metallic element to non-metallic element in a second barrier layer and a third barrier layer.

The present disclosure provides a DNA-targeting RNA that comprises a targeting sequence and, together with a modifying polypeptide, provides for site-specific modification of a target DNA and/or a polypeptide associated with the target DNA. The present disclosure further provides site-specific modifying polypeptides. The present disclosure further provides methods of site-specific modification of a target DNA and/or a polypeptide associated with the target DNA The present disclosure provides methods of modulating transcription of a target nucleic acid in a target cell, generally involving contacting the target nucleic acid with an enzymatically inactive Cas9 polypeptide and a DNA-targeting RNA. Kits and compositions for carrying out the methods are also provided. The present disclosure provides genetically modified cells that produce Cas9; and Cas9 transgenic non-human multicellular organisms.

An epitaxial wafer that includes a silicon wafer and an epitaxial layer on the silicon wafer. The silicon wafer contains hydrogen that has a concentration profile including a first peak and a second peak. A hydrogen peak concentration of the first peak and a hydrogen peak concentration of the second peak are each not less than 1×10.sup.17 atoms/cm.sup.3.

A method for growing a transition metal dichalcogenide layer involves arranging a substrate having a first transition metal contained pad is arranged in a chemical vapor deposition chamber. A chalcogen contained precursor is arranged upstream of the substrate in the chemical vapor deposition chamber. The chemical vapor deposition chamber is heated for a period of time during which a transition metal dichalcogenides layer, containing transition metal from the first transition metal contained pad and chalcogen from the chalcogen contained precursor, is formed in an area adjacent to the first transition metal contained pad.

An epitaxial growth device is provided, which includes an induction coil and a reaction body, and the induction coil is disposed along a circumferential direction of the reaction body; and the reaction body includes a heating base and a plurality of trays, wherein the heating base includes a plurality of workspaces, the plurality of trays are disposed in the plurality of workspaces, respectively, and each of the plurality of trays is disposed in a corresponding workspace; wherein each of the plurality of trays is configured to support a substrate, and each of the plurality of trays is capable of independently rotating relative to the heating base.

A substrate processing apparatus includes: a substrate retainer configured to support a substrate; a heat-insulating unit; a transfer chamber; and a gas supply mechanism configured to supply a gas into the transfer chamber, the gas supply mechanism including: a first gas supply mechanism configured to supply the gas into an upper region of the transfer chamber, where the substrate retainer is disposed such that the gas flows horizontally through the upper region; and a second gas supply mechanism configured to supply the gas into a lower region of the transfer chamber, where the heat-insulating unit is provided such that the gas flows downward through the lower region, wherein the first gas supply mechanism and the second gas supply mechanism are disposed along a first sidewall of the transfer chamber, and the second gas supply mechanism is disposed lower than the first gas supply mechanism.