Patent classifications
H01L21/02452
MULTI-GATE TRANSISTORS AND METHODS OF FORMING THE SAME
The present disclosure provides a semiconductor structure and a method of forming the same. A semiconductor structure according to the present disclosure includes a plurality of nanostructures disposed over a substrate and a gate structure wrapping around each of the plurality of nanostructure. Each of the plurality of nanostructures includes a channel layer sandwiched between two cap layers along a direction perpendicular to the substrate.
Methods for selective deposition of doped semiconductor material
Methods and systems for selectively depositing material, such as doped semiconductor material, are disclosed. An exemplary method includes providing a substrate, comprising a first area comprising a first material and a second area comprising a second material, selectively depositing a first doped semiconductor layer overlying the first material relative to the second material and selectively depositing a second doped semiconductor layer overlying the first doped semiconductor layer relative to the second material.
SOURCE/DRAIN FEATURES OF MULTI-GATE DEVICES
Methods and semiconductor structures are provided. A method according to the present disclosure includes forming, over a substrate, a fin-shaped structure that includes a plurality of channel layers interleaved by a plurality of sacrificial layers, recessing a source/drain region of the fin-shaped structure to form a source/drain recess that extends into the substrate and exposes a portion of the substrate, selectively and partially recessing sidewalls of the plurality of sacrificial layers to form inner spacer recesses, forming inner spacers in the inner spacer recesses, selectively forming a buffer semiconductor layer on the exposed portion of the substrate, selectively depositing a first epitaxial layer on sidewalls of the plurality of channel layer and the buffer semiconductor layer such that a top surface of the buffer semiconductor layer is completely covered by the first epitaxial layer, and depositing a second epitaxial layer over the first epitaxial layer and the inner spacers.
FORMATION OF EPITAXIAL LAYERS VIA DISLOCATION FILTERING
A process for forming a thick defect-free epitaxial layer is disclosed. The process may comprise forming a buffer layer and a sacrificial layer prior to forming the thick defect-free epitaxial layer. The sacrificial layer and the thick defect-free epitaxial layer may be formed of the same material and at the same process conditions.
QUANTUM HETEROSTRUCTURES, RELATED DEVICES AND METHODS FOR MANUFACTURING THE SAME
There is provided a quantum heterostructure and related devices, as well as methods for manufacturing the same. The quantum heterostructure includes a stack of coextending GeSn buffer layers and each GeSn buffer layer has a different Sn content one from another. The quantum heterostructure also includes a quantum well extending over the stack of coextending GeSn buffer layers, the quantum well comprising a highly tensile-strained layer, the highly tensile-strained layer comprising at least one group IV element and having a strain greater than or equal to 1%. The quantum heterostructure is compatible with silicon-based processing, manufacturing, and technologies. The method includes changing a reactor temperature and varying a molar fraction of an Sn-based precursor to achieve a stack of coextending GeSn buffer layers, each having a different Sn composition, on a substrate provided inside the reactor chamber and forming the quantum well over the stack of coextending GeSn buffer layers.
Nanowire and method of fabricating the same
A method of forming a nanowire includes providing a substrate. The substrate is etched to form at least one fin. Subsequently, a first epitaxial layer is formed on an upper portion of the fin. Later, an undercut is formed on a middle portion the fin. A second epitaxial layer is formed to fill into the undercut. Finally, the fin, the first epitaxial layer and the second epitaxial layer are oxidized to condense the first epitaxial layer and the second epitaxial layer into a germanium-containing nanowire.
III-N MULTICHIP MODULES AND METHODS OF FABRICATION
A device includes a layer including a first III-Nitride (III-N) material, a channel layer including a second III-N material, a release layer including nitrogen and a transition metal, where the release layer is between the first III-N material and the second III-N material. The device further includes a polarization layer including a third III-N material above the release layer, a gate structure above the polarization layer, a source structure and a drain structure on opposite sides of the gate structure where the source structure and the drain structure each include a fourth III-N material. The device further includes a source contact on the source structure and a drain contact on the drain structure.
Method for forming semiconductor device having boron-doped germanium tin epitaxy structure
A method includes forming a first semiconductor layer over a substrate; forming a second semiconductor layer over the first semiconductor layer; forming a dummy gate structure over the second semiconductor layer; performing an etching process to form a recess in the first and second semiconductor layers; forming a epitaxy structure over in the recess, wherein the epitaxy structure is in contact with the first and second semiconductor layers; performing a solid phase diffusion process to form a doped region in the epitaxy structure, in which the doped region is in contact with the second semiconductor layer and is separated from the first semiconductor layer; and replacing the dummy gate structure with a metal gate structure.
III-N MULTICHIP MODULES AND METHODS OF FABRICATION
A device includes a layer including a first III-Nitride (III-N) material, a channel layer including a second III-N material, a release layer including nitrogen and a transition metal, where the release layer is between the first III-N material and the second III-N material. The device further includes a polarization layer including a third III-N material above the release layer, a gate structure above the polarization layer, a source structure and a drain structure on opposite sides of the gate structure where the source structure and the drain structure each include a fourth III-N material. The device further includes a source contact on the source structure and a drain contact on the drain structure.
METHODS OF FORMING SILICON GERMANIUM STRUCTURES
Methods for forming structures that include forming a heteroepitaxial layer on a substrate are disclosed. The presently disclosed methods comprise epitaxially forming a buffer layer on the substrate. The substrate has a substrate composition. The buffer layer has a buffer layer composition. The buffer layer composition is substantially identical to the substrate composition. The presently disclosed methods further comprise epitaxially forming a heteroepitaxial layer on the buffer layer. The heteroepitaxial layer has a heteroepitaxial layer composition which is different from the substrate composition.