An epitaxial structure and a manufacturing method thereof, and a light-emitting diode (LED) device are provided. The epitaxial structure includes an N-type semiconductor layer, a multiple quantum well (MQW) active layer, and a P-type semiconductor layer sequentially stacked in a growth direction. The MQW active layer includes a front MQW active layer and a back MQW active layer sequentially stacked in the growth direction. The front MQW active layer includes at least two groups of first quantum barrier layers and first quantum well layers alternately stacked. The back MQW active layer includes at least two groups of second quantum barrier layers and second quantum well layers alternately stacked. A content of an aluminum (Al) component in each second quantum well layer is gradually increased in the growth direction, and a content of a gallium (Ga) component in each second quantum well layer is gradually decreased in the growth direction.

A method for making a device. The method comprises forming a buffer layer on a substrate; forming a periodically doped layer on the buffer layer; forming one or more wires on the periodically doped layer, the wires being chosen from nanowires and microwires; and introducing porosity into the periodically doped layer to form a porous distributed Bragg reflector (DBR). Various devices that can be made by the method are also disclosed.

A semiconductor structure (100) comprising: a substrate (102), a first layer (106) of Al.sub.XGa.sub.YIn.sub.(1−X−Y)N disposed on the substrate, stacks (107, 109) of several second and third layers (108, 110) alternating against each other, between the substrate and the first layer, a fourth layer (112) of Al.sub.XGa.sub.YIn.sub.(1−X−Y)N, between the stacks, a relaxation layer of AlN disposed between the fourth layer and one of the stacks, and, in each of the stacks: the level of Ga of the second layers increases from one layer to the next in a direction from the substrate to the first layer, the level of Ga of the third layers is constant or decreasing from one layer to the next in said direction, the average mesh parameter of each group of adjacent second and third layers increasing from one group to the next in said direction, the thickness of the second and third layers is less than 5 nm.

A recess and a recess are formed at places where a threading dislocation and a threading dislocation reach a surface of a third semiconductor layer. A through-hole and a through-hole are formed in a second semiconductor layer under places of the recess and the recess, the through-hole and the through-hole extending through the second semiconductor layer. A first semiconductor layer is oxidized through the recess, the recess, the through-hole, and the through-hole to form an insulation film that covers a lower surface of the second semiconductor layer. The third semiconductor layer is subjected to crystal regrowth.

Transdermal microneedles continuous monitoring system is provided. The continuous system monitoring includes a substrate, a microneedle unit, a signal processing unit and a power supply unit. The microneedle unit at least comprises a first microneedle set used as a working electrode and a second microneedle set used as a reference electrode, the first and second microneedle sets arranging on the substrate. Each microneedle set comprises at least a microneedle. The first microneedle set comprises at least a sheet having a through hole on which a barbule forms at the edge. One of the sheets provides the through hole from which the barbules at the edge of the other sheets go through, and the barbules are disposed separately.

Provided is a polycrystalline ceramic substrate to be bonded to a compound semiconductor substrate with a bonding layer interposed therebetween, wherein at least one of relational expression (1) 0.7<α.sub.1/α.sub.2<0.9 and relational expression (2) 0.7<α.sub.3/α.sub.4<0.9 holds, where α.sub.1 represents a linear expansion coefficient of the polycrystalline ceramic substrate at 30° C. to 300° C. and α.sub.2 represents a linear expansion coefficient of the compound semiconductor substrate at 30° C. to 300° C., and α.sub.3 represents a linear expansion coefficient of the polycrystalline ceramic substrate at 30° C. to 1000° C. and α.sub.4 represents a linear expansion coefficient of the compound semiconductor substrate at 30° C. to 1000° C.

Embodiments herein describe techniques for a thin-film transistor (TFT) above a substrate. The transistor includes a contact electrode having a conductive material above the substrate, an epitaxial layer above the contact electrode, and a channel layer including a channel material above the epitaxial layer and above the contact electrode. The channel layer is in contact at least partially with the epitaxial layer. A conduction band of the channel material and a conduction band of a material of the epitaxial layer are substantially aligned with an energy level of the conductive material of the contact electrode. A bandgap of the material of the epitaxial layer is smaller than a bandgap of the channel material. Furthermore, a gate electrode is above the channel layer, and separated from the channel layer by a gate dielectric layer. Other embodiments may be described and/or claimed.

A single crystal semiconductor structure includes: an amorphous substrate; a single crystal semiconductor layer provided on the amorphous substrate; and a thin orienting film provided between the amorphous substrate and the single crystal semiconductor layer, wherein the thin orienting film is a single crystal thin film, and the thin orienting film has a non-zero thickness that is equal to or less than 10 times a critical thickness h.sub.c.

A single crystal semiconductor structure includes: an amorphous substrate; a single crystal semiconductor layer provided on the amorphous substrate; and a thin orienting film provided between the amorphous substrate and the single crystal semiconductor layer, wherein the thin orienting film is a single crystal thin film, and the thin orienting film has a non-zero thickness that is equal to or less than 10 times a critical thickness h.sub.c.

A method for forming a material having a Perovskite single crystal structure includes alternately growing, on a substrate, each of a plurality of first layers and each of a plurality of second layers having compositions different from the plurality of first layers and forming a material having a Perovskite single crystal structure by annealing the plurality of first layers and the plurality of second layers.