A process of making sensors and sensor arrays that has the ability to manipulate of the morphology or flow of an applied drop or sample over the sensor array surface at any point in the patterning process and sensors and sensor arrays having increased sensitivity and limits of detection. In addition, said process can provided real time notification of any centerline deviation. Such production process can be adjusted in real time. Thus, large numbers of units can be made—even in millions of per day—with few if any out of specification units being produced. Such process does not require large-scale clean rooms and is easily configurable.

A display apparatus and a method of manufacturing the same are provided. According to an embodiment, a display apparatus includes: a substrate; a thin-film transistor located on the substrate; and a buffer layer, a conductive layer, and an insulating layer sequentially located from the substrate between the substrate and the thin-film transistor, and a thickness of the insulating layer is less than a thickness of the buffer layer.

A method for growing a semiconductor material over a Si-based substrate includes providing the Si-based substrate; growing a monocrystalline refractory-metal ceramic film directly over the Si-based substrate; and depositing a semiconductor film directly over the monocrystalline refractory-metal ceramic film. The monocrystalline refractory-metal ceramic film has a thickness less than 300 nm.

A method of manufacturing a semiconductor device includes: forming first to third preliminary active patterns on a substrate to have different intervals therebetween, forming first and second field insulating layers between the first and second preliminary active patterns and between the second and third preliminary active patterns, respectively, and forming first to third gate electrodes respectively on first to third active patterns formed based on the first to third preliminary active patterns, separated by first and second gate isolation structures.

This invention in one aspect relates to a method of synthesizing a self-assembled mixed-dimensional heterostructure including 2D metallic borophene and 1D semiconducting armchair-oriented graphene nanoribbons (aGNRs). The method includes depositing boron on a substrate to grow borophene thereon at a substrate temperature in an ultrahigh vacuum (UHV) chamber; sequentially depositing 4,4″-dibromo-p-terphenyl on the borophene grown substrate at room temperature in the UHV chamber to form a composite structure; and controlling multi-step on-surface coupling reactions of the composite structure to self-assemble a borophene/graphene nanoribbon mixed-dimensional heterostructure. The borophene/aGNR lateral heterointerfaces are structurally and electronically abrupt, thus demonstrating atomically well-defined metal-semiconductor heterojunctions.

A method of manufacturing a semiconductor nanowire semiconductor device is described. The method includes forming an amorphous channel material layer on a substrate, patterning the channel material layer to form semiconductor nanowires extending in a lateral direction on the substrate, and forming a cover layer covering an upper of the semiconductor nanowire. The cover layer and the nanowire are patterned to form a trench exposing a side section of an one end of the semiconductor nanowire and a catalyst material layer is formed in contact with a side surface of the semiconductor nanowire, and metal induced crystallization (MIC) by heat treatment is performed to crystallize the semiconductor nanowire in a length direction of the nanowire from the one end of the semiconductor nanowire in contact with the catalyst material.

Structures described herein may include mechanically bonded interlayers for formation between a first Group III-V semiconductor layer and a second semiconductor layer. The mechanically bonded interlayers provide reduced lattice strain by strain balancing between the Group III-V semiconductor layer and the second semiconductor layer, which may be silicon.

A vertical nanowire semiconductor device manufactured by a method of manufacturing a vertical nanowire semiconductor device is provided. The vertical nanowire semiconductor device includes a substrate, a first conductive layer in a source or drain area formed above the substrate, a semiconductor nanowire of a channel area vertically upright with respect to the substrate on the first conductive layer, wherein a crystal structure thereof is grown in <111> orientation, a second conductive layer of a drain or source area provided on the top of the semiconductor nanowire, a metal layer on the second conductive layer, a NiSi.sub.2 contact layer between the second conductive layer and the metal layer, a gate surrounding the channel area of the vertical nanowire, and a gate insulating layer located between the channel area and the gate.

The present invention relates to a method for manufacturing a diamond substrate, and more particularly, to a method of growing diamond after forming a structure of an air gap having a crystal correlation with a lower substrate by heat treatment of a photoresist pattern and an air gap forming film material on a substrate such as sapphire (Al.sub.2O.sub.3). Through such a method, a process is simplified and the cost is lowered when large-area/large-diameter single crystal diamond is heterogeneously grown, stress due to differences in a lattice constant and a coefficient of thermal expansion between the heterogeneous substrate and diamond is relieved, and an occurrence of defects or cracks is reduced even when a temperature drops, such that a high-quality single crystal diamond substrate may be manufactured and the diamond substrate may be easily self-separated from the heterogeneous substrate.

A method of making a crystallographically-oriented metallic film with a two-dimensional crystal layer, comprising the steps of providing a metal film on a substrate, transferring a two-dimensional crystal layer onto the metal film and forming a two-dimensional crystal layer on metal film complex, heating the two-dimensional crystal layer on metal film complex, and forming a crystallographically-oriented metallic film with a two-dimensional crystal layer. A crystallographically-oriented metallic film with a two-dimensional crystal layer, comprising a substrate, a metal film on the substrate, a two-dimensional crystal layer on the metal film on the substrate, and a tunable microstructure within the porous metal/two-dimensional crystal layer on the substrate, wherein the metal film has crystallographic registry to the two-dimensional crystal layer.