The present disclosure provides a semiconductor structure and a manufacturing method thereof, and relates to the technical field of semiconductors. The semiconductor structure includes: a base, including a doped region; a recess, located in the doped region; and a gradient layer, filling the recess, wherein a doping concentration of the gradient layer varies gradually from a bottom of the recess upwards.

A method for forming layers with silicon is disclosed. The layers may be created by positioning a substrate within a processing chamber, heating the substrate to a first temperature between 300 and 500° C. and introducing a first precursor into the processing chamber to deposit a first layer. The substrate may be heated to a second temperature between 400 and 600° C.; and, a second precursor may be introduced into the processing chamber to deposit a second layer. The first and second precursor may comprise silicon atoms and the first precursor may have more silicon atoms per molecule than the second precursor.

A method and a wafer processing furnace for forming an epitaxial stack on a plurality of substrates is provided. In a preferred embodiment, the method comprises providing the plurality of substrates to a process chamber. A plurality of deposition cycles is executed, thereby forming the epitaxial stack on the plurality of substrates. The epitaxial stack comprises a plurality of epitaxial pairs, wherein the epitaxial pairs each comprises a first epitaxial layer and a second epitaxial layer, the second epitaxial layer being different from the first epitaxial layer. Each deposition cycle comprises a first deposition pulse and a second deposition pulse. The first deposition pulse comprises a provision of a first reaction gas mixture to the process chamber, thereby forming the first epitaxial layer. The second deposition pulse comprises a provision of a second reaction gas mixture to the process chamber, thereby forming the second epitaxial layer. The first deposition pulse or the second deposition pulse further comprises a provision of a dopant precursor gas to the process chamber.

A transistor structure is disclosed. The transistor structure includes a dielectric layer that has a thinner portion over a first doped well and a second doped well, and a thicker portion adjacent the thinner portion and over the second doped well. The thicker portion has a height greater than the thinner portion above the doped wells. The transistor includes a first gate structure on the thinner portion and a second gate structure on the thicker portion of the dielectric layer. The transistor may include a third gate structure on the thicker portion.

A method for forming a Ga-doped SiGe layer comprises depositing, in the presence of a C-containing Ga precursor, Ga-doped SiGe on a substrate, thereby forming a first portion of the Ga-doped SiGe layer. The method further comprises depositing, in the absence of the C-containing Ga precursor, SiGe on the first portion, thereby forming a second portion of the Ga-doped SiGe layer.

A method of forming source/drain features in a FinFET device includes providing a fin formed over a substrate and a gate structure formed over a fin, forming a recess in the fin adjacent to the gate structure, forming a first epitaxial layer in the recess, forming a second epitaxial layer over the first epitaxial layer, and forming a third epitaxial layer over the second epitaxial layer. The second epitaxial layer may be doped with a first element, while one or both of the first and the third epitaxial layer includes a second element different from the first element. One or both of the first and the third epitaxial layer may be formed by a plasma deposition process.

A doped diamond semiconductor and method of production using a laser is disclosed herein. As disclosed, a dopant and/or a diamond or sapphire seed material may be added to a graphite based ablative layer positioned below a confinement layer, the ablative layer also being graphite based and positioned above a backing layer, to promote formation of diamond particles having desirable semiconductor properties via the action of a laser beam upon the ablative layer. Dopants may be incorporated into the process to activate the reaction sought to produce a material useful in production of a doped semiconductor or a doped conductor suitable for the purpose of modulating the electrical, thermal or quantum properties of the material produced. As disclosed, the diamond particles formed by either the machine or method of confined pulsed laser deposition disclosed may be arranged as semiconductors, electrical components, thermal components, quantum components and/or integrated circuits.

A method of forming source/drain features in a FinFET device includes providing a fin formed over a substrate and a gate structure formed over a fin, forming a recess in the fin adjacent to the gate structure, forming a first epitaxial layer in the recess, forming a second epitaxial layer over the first epitaxial layer, and forming a third epitaxial layer over the second epitaxial layer. The second epitaxial layer may be doped with a first element, while one or both of the first and the third epitaxial layer includes a second element different from the first element. One or both of the first and the third epitaxial layer may be formed by a plasma deposition process.

An integrated circuit (IC) structure with a nanowire power switch device and a method of forming the IC structure are disclosed. The IC structure includes a front end of line (FEOL) device layer having a plurality of active devices, a first back end of line (BEOL) interconnect structure on the (FEOL) device layer, and a nanowire switch on the first BEOL interconnect structure. A first end of the nanowire switch is connected to an active device of the plurality of active devices through the first BEOL interconnect structure. The IC structure further includes a second BEOL interconnect structure on the nanowire switch. A second end of the nanowire switch is connected to a power source through the second BEOL interconnect structure and the second end is opposite to the first end.

Embodiments of the present disclosure generally relate to methods for forming epitaxial layers on a semiconductor device. In one or more embodiments, methods include removing oxides from a substrate surface during a cleaning process, flowing a processing reagent containing a silicon source and exposing the substrate to the processing reagent during an epitaxy process, and stopping the flow of the processing reagent. The method also includes flowing a purging gas and pumping residues from the processing system, stopping the flow of the purge gas, flowing an etching gas and exposing the substrate to the etching gas. The etching gas contains hydrogen chloride and at least one germanium and/or chlorine compound. The method further includes stopping the flow of the at least one compound while continuing the flow of the hydrogen chloride and exposing the substrate to the hydrogen chloride and stopping the flow of the hydrogen chloride.