A method of manufacturing a semiconductor device includes providing a substrate structure. The substrate structure includes a conductive layer and a plurality of nanopillars spaced apart from each other overlying the conductive layer. Each nanopillar includes a first semiconductor layer and a second semiconductor layer on the first semiconductor layer. The first semiconductor layer and the second semiconductor layer have different conductivity types. The method also includes forming a graphene layer overlying the plurality of nanopillars. The graphene layer is connected to each of the plurality of nanopillars.

In various embodiments a method for manufacturing a metallization layer on a substrate is provided, wherein the method may include providing a structured layer of a catalyst material on the substrate, the catalyst material may include a first layer of material arranged over the substrate and a second layer of material arranged over the first layer of material, wherein the structured layer of catalyst material having a first set of regions including the catalyst material over the substrate and a second set of regions free of the catalyst material over the substrate, and forming a plurality of groups of nanotubes over the substrate, each group of the plurality of groups of nanotubes includes a plurality of nanotubes formed over a respective region in the first set of regions.

A semiconductor device includes a first PMOS transistor, a first NMOS transistor, and a second NMOS transistor connected to an output node of the first PMOS and NMOS transistors. The first PMOS transistor includes first nanowires, first source and drain regions on opposite sides of each first nanowire, and a first gate completely surrounding each first nanowire. The first NMOS transistor includes second nanowires, second source and drain regions on opposite sides of each second nanowire, and a second gate extending from the first gate and completely surrounding each second nanowire. The second NMOS transistor includes third nanowires, third source and drain regions on opposite sides of each third nanowire, and a third gate, separated from the first and second gates, and completely surrounding each third nanowire. A number of third nanowires is greater than that of first nanowires. The first and second gates share respective first and second nanowires.

Provided are a pellicle film, a pellicle, an original plate for exposure, an exposure device, a method of producing a semiconductor device, and a method of producing a pellicle, the pellicle film containing carbon nanotubes having a silicon carbide layer in which at least a part of carbon is substituted with silicon at least on a surface layer side.

A method includes forming a first low-dimensional layer over an isolation layer, forming a first insulator over the first low-dimensional layer, forming a second low-dimensional layer over the first insulator, forming a second insulator over the second low-dimensional layer, and patterning the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator into a protruding fin. Remaining portions of the first low-dimensional layer, the first insulator, the second low-dimensional layer, and the second insulator form a first low-dimensional strip, a first insulator strip, a second low-dimensional strip, and a second insulator strip, respectively. A transistor is then formed based on the protruding fin.

A method for obtaining metallic carbon nanotubes is provided. An insulating substrate comprising hollow portions and non-hollow portions is provided. A plurality of electrodes is formed on a surface of the non-hollow portions. A plurality of carbon nanotubes is formed on a surface of the insulating substrate, and the carbon nanotubes stretch across the hollow portions. The insulating substrate, the plurality of electrodes and the carbon nanotubes are placed into a cavity, and the cavity is evacuated. A voltage is applied between any two electrodes, and photos of carbon nanotubes suspended between the two electrodes are taken. In the photo, darker ones are semiconducting carbon nanotubes, and brighter ones are metallic carbon nanotubes. Finally, the semiconducting carbon nanotubes are removed.

A memory device includes a bottom electrode, an insulating layer, and a top electrode. The bottom electrode includes a plurality of carbon nanotubes. The insulating layer is disposed over the plurality of carbon nanotubes. The top electrode includes a graphene layer separated from the plurality of carbon nanotubes by the insulating layer.

A method for forming nanostructures including introducing a hollow shell into a reactor. The hollow shell has catalyst nanoparticles exposed on its interior surface. The method also includes introducing a precursor into the reactor to grow nanostructures from the interior surface of the hollow shell from the catalyst nanoparticles.

The invention relates to a method for manufacture of an electrical contact on a structure (10) made of an anisotropic material NA which exhibits an anisotropic electrical conductivity, where the structure (10) exhibits an axial electrical conductivity along a first axis XX′ of the structure (10) and an orthogonal conductivity along a direction YY′ orthogonal to the first axis XX′ of the structure (10), where the orthogonal conductivity is less than the axial conductivity, where the method comprises: a step for the formation of a conductive electrode (20), with an initial thickness Ei, comprising a species M, on a first surface (30) of the structure (10), where the first surface (30) is orthogonal to the orthogonal direction YY′; the method being characterized in that the step for the formation of the conductive electrode (20) is followed by a step for implantation of species X through the conductive electrode (20), into the structure (10).

A nano-vacuum tube (NVT) transistor comprising a source having a knife edge, a drain, and a channel formed between the source and the drain, the channel having a width to provide a pseudo-vacuum in a normal atmosphere. The NVT transistor utilizing a space charge plasma formed at the knife edge within the channel.