H01L21/02617

SELF-ASSEMBLED BOROPHENE/GRAPHENE NANORIBBON MIXED-DIMENSIONAL HETEROSTRUCTURES AND METHOD OF SYNTHESIZING SAME
20230008590 · 2023-01-12 ·

This invention in one aspect relates to a method of synthesizing a self-assembled mixed-dimensional heterostructure including 2D metallic borophene and 1D semiconducting armchair-oriented graphene nanoribbons (aGNRs). The method includes depositing boron on a substrate to grow borophene thereon at a substrate temperature in an ultrahigh vacuum (UHV) chamber; sequentially depositing 4,4″-dibromo-p-terphenyl on the borophene grown substrate at room temperature in the UHV chamber to form a composite structure; and controlling multi-step on-surface coupling reactions of the composite structure to self-assemble a borophene/graphene nanoribbon mixed-dimensional heterostructure. The borophene/aGNR lateral heterointerfaces are structurally and electronically abrupt, thus demonstrating atomically well-defined metal-semiconductor heterojunctions.

Graphene LHFETS (lateral heterostructure field effect transistors) on SI compatible with CMOS BEOL process

A field effect transistor includes a substrate, a passivation layer on the substrate forming a passivated substrate, wherein the passivation layer is inert to XeF.sub.2, and a graphene lateral heterostructure field effect transistor (LHFET) on the passivated substrate.

THERMOREFLECTANCE ENHANCEMENT COATINGS AND METHODS OF MAKING AND USE THEREOF
20220404204 · 2022-12-22 ·

Disclosed herein are thermoreflectance enhancement coatings and methods of making and use thereof.

Method semiconductor device fabrication with improved epitaxial source/drain proximity control

A semiconductor device includes a substrate, a first fin extending from the substrate, a first gate structure over the substrate and engaging the first fin, and a first epitaxial feature partially embedded in the first fin and raised above a top surface of the first fin. The semiconductor device further includes a second fin extending from the substrate, a second gate structure over the substrate and engaging the second fin, and a second epitaxial feature partially embedded in the second fin and raised above a top surface of the second fin. A first depth of the first epitaxial feature embedded into the first fin is smaller than a second depth of the second epitaxial feature embedded into the second fin.

LASER INDUCED FORWARD TRANSFER OF 2D MATERIALS

A system and method for performing is laser induced forward transfer (LIFT) of 2D materials is disclosed. The method includes generating a receiver substrate, generating a donor substrate, wherein the donor substrate comprises a back surface and a front surface, applying a coating to the front surface, wherein the coating includes donor material, aligning the front surface of the donor substrate to be parallel to and facing the receiver substrate, wherein the donor material is disposed adjacent to the target layer, and irradiating the coating through the back surface of the donor substrate with one or more laser pulses produced by a laser to transfer a portion of the donor material to the target layer. The donor material may include Bi.sub.2S.sub.3-xS.sub.x, MoS.sub.2, hexagonal boron nitride (h-BN) or graphene. The method may be used to create touch sensors and other electronic components.

Single crystal semiconductor structure and method of fabricating the same

A single crystal semiconductor structure includes: an amorphous substrate; a single crystal semiconductor layer provided on the amorphous substrate; and a thin orienting film provided between the amorphous substrate and the single crystal semiconductor layer, wherein the thin orienting film is a single crystal thin film, and the thin orienting film has a non-zero thickness that is equal to or less than 10 times a critical thickness h.sub.c.

SINGLE CRYSTAL SEMICONDUCTOR STRUCTURE AND METHOD OF FABRICATING THE SAME

A single crystal semiconductor structure includes: an amorphous substrate; a single crystal semiconductor layer provided on the amorphous substrate; and a thin orienting film provided between the amorphous substrate and the single crystal semiconductor layer, wherein the thin orienting film is a single crystal thin film, and the thin orienting film has a non-zero thickness that is equal to or less than 10 times a critical thickness h.sub.c.

Methods and apparatus for reducing as-deposited and metastable defects in Amorphousilicon
11502217 · 2022-11-15 ·

A method and apparatus for reducing as-deposited and metastable defects relative to amorphous silicon (a-Si) thin films, its alloys and devices fabricated therefrom that include heating an earth shield positioned around a cathode in a parallel plate plasma chemical vapor deposition chamber to control a temperature of a showerhead in the deposition chamber in the range of 350° C. to 600° C. An anode in the deposition chamber is cooled to maintain a temperature in the range of 50° C. to 450° C. at the substrate that is positioned at the anode. In the apparatus, a heater is embedded within the earth shield and a cooling system is embedded within the anode.

Method and device for decreasing generation of surface oxide of aluminum nitride
11597999 · 2023-03-07 · ·

The present disclosure relates to a method and device for decreasing generation of surface oxide of aluminum nitride. In a physical vapor deposition process, the aluminum nitride is deposited on a substrate in a deposition chamber to form an aluminum nitride coated substrate. A cooling chamber and a cooling load lock module respectively perform a first stage cooling and a second stage cooling on the aluminum nitride coated substrate in vacuum environments, so as to prevent the aluminum nitride coated substrate with the high temperature from being exposed in an atmosphere environment to generate the surface oxide. The method and device for decreasing the generation of the surface oxide of the aluminum nitride can further eliminate crystal defects caused by that gallium nitride is deposited on the surface oxide of the aluminum nitride in the next process.

MEMORY DEVICE INCLUDING MULTIPLE DECKS OF MEMORY CELLS AND PILLARS EXTENDING THROUGH THE DECKS

Some embodiments include apparatuses and methods of forming the apparatuses. One of the apparatuses includes a first deck located over a substrate, and a second deck located over the first deck, and pillars extending through the first and second decks. The first deck includes first memory cells, first control gates associated with the first memory cells, and first conductive paths coupled to the first control gates. The second conductive paths include second conductive pads located on a first level of the apparatus over the substrate. The second deck includes second memory cells, second control gates associated with the second memory cells, and second conductive paths coupled to the second control gates. The second conductive paths include second conductive pads located on a second level of the apparatus. The first and second conductive pads having lengths in a direction perpendicular to a direction from the first deck to the second deck.