Provides a method for adjusting a thermal field of silicon carbide single crystal growth, and steps comprise: (A) screening a silicon carbide source, and filling into a bottom of a graphite crucible; (B) placing a guide inside the graphite crucible; (C) placing a rigid heat conductive material on the guide, so that a gap between the guide and a crucible wall of the graphite crucible is reduced; (D) fixing a seed crystal on a top of the graphite crucible; (E) placing the graphite crucible equipped with the silicon carbide source and the seed crystal in an induction high-temperature furnace used by physical vapor transport method; (F) performing a silicon carbide crystal growth process; and (G) obtaining a silicon carbide single crystal.

Pedestal assemblies, purge rings for pedestal assemblies, and processing methods for increasing residence time of an edge purge gas in heated pedestal assemblies are described. Purge rings have an inner diameter face and an outer diameter face defining a thickness of the purge ring, a top surface and a bottom surface defining a height of the purge ring, and a thermal expansion feature. Purge rings comprise a plurality of apertures extending through the thickness and aligned circumferentially with a plurality of circumferentially spaced purge outlets in a substrate support.

A method for filling recessed features with a low-resistivity metal. The method includes providing a patterned substrate containing a recessed feature formed in a first layer and a second layer that is exposed in the recessed feature, and pre-treating the substrate with a surface modifier that increases metal deposition selectivity on the second layer relative to on the first layer, depositing a metal layer on the substrate by vapor phase deposition, where the metal layer is preferentially deposited on the second layer in the recessed feature, and removing metal nuclei deposited on the first layer, including on a field area and on sidewalls of the first layer in the recessed feature, to selectively form the metal layer on the second layer in the recessed feature. The steps of pre-treating, depositing and removing may be repeated at least once to increase a thickness of the metal layer in the recessed feature.

A method of making a transistor for an integrated circuit includes providing a substrate and forming a dummy gate for the transistor within a gate trench on the substrate. The gate trench includes sidewalls, a trench bottom, and a trench centerline extending normally from a center portion of the trench bottom. The dummy gate is removed from the gate trench. A gate dielectric layer is disposed within the gate trench. A gate work-function metal layer is disposed over the gate dielectric layer, the work-function metal layer including a pair of corner regions proximate the trench bottom. An angled implantation process is utilized to implant a work-function tuning species into the corner regions at a tilt angle relative to the trench centerline, the tilt angle being greater than zero.

Methods and apparatuses to produce graphene and nanoparticle catalysts supported on graphene without the use of reducing agents, and with the concomitant production of heat, are provided. The methods and apparatuses employ radiant energy to reduce (deoxygenate) graphite oxide (GO) to graphene, or to reduce a mixture of GO plus one or more metals to produce nanoparticle catalysts supported on graphene. Methods and systems to generate and utilize heat that is produced by irradiating GO, graphene and their metal and semiconductor nanocomposites with visible, infrared and/or ultraviolet radiation, e.g. using sunlight, lasers, etc. are also provided.

A method of manipulating deposition rates of poly-silicon and a method of manufacturing a silicon-germanium (SiGe) heterojunction bipolar transistor (HBT) device are provided. The method of manipulating deposition rates of poly-silicon includes: providing a substrate, where a first surface of the substrate includes at least two of an oxide material region, a silicon nitride material region and a silicon material region; performing a first treatment on the first surface of the substrate, so as to manipulate the deposition rates of poly-silicon on different regions of the first surface to be closer; and forming a poly-silicon layer on the first surface of the substrate.

Embodiments of process kits for use in a process chamber are provided herein. In some embodiments, a cover ring for use in a process chamber includes: an annular body that includes an upper surface and a lower surface, an inner lip extending radially inward and downward from the annular body, and a plurality of protrusions extending downward from the inner lip and disposed at regular intervals along the inner lip, wherein lowermost surfaces of the plurality of protrusions together define a planar substrate contact surface.

A method of forming a semiconductor structure includes forming a first material over a base material by vapor phase epitaxy. The first material has a crystalline portion and an amorphous portion. The amorphous portion of the first material is removed by abrasive planarization. At least a second material is formed by vapor phase epitaxy over the crystalline portion of first material. The second material has a crystalline portion and an amorphous portion. The amorphous portion of the second material is removed by abrasive planarization. A semiconductor structure formed by such a method includes the substrate, the first material, the second material, and optionally, an oxide material between the first material and the second material. The substrate, the first material, and the second material define a continuous crystalline structure. Semiconductor structures, memory devices, and systems are also disclosed.

Strain relief trenches may be formed in a substrate prior to growth of an epitaxial layer on the substrate. The trenches may reduce the stresses and strains on the epitaxial layer that occur during the epitaxial growth process due to differences in material properties (e.g., lattice mismatches, differences in thermal expansion coefficients, and/or the like) between the epitaxial layer material and the substrate material. The stress and strain relief provided by the trenches may reduce or eliminate cracks and/or other types of defects in the epitaxial layer and the substrate, may reduce and/or eliminate bowing and warping of the substrate, may reduce breakage of the substrate, and/or the like. This may increase the center-to-edge quality of the epitaxial layer, may permit epitaxial layers to be grown on larger substrates, and/or the like.

A method of filling a recess according to one embodiment of the present disclosure comprises heating an amorphous semiconductor film without crystallizing the amorphous semiconductor film by radiating laser light to the amorphous semiconductor film embedded in the recess.