A transistor device and a method for producing thereof are disclosed. The transistor device includes: a SiC semiconductor body that includes a first semiconductor layer; a plurality of trenches each extending from a first surface of the first semiconductor layer into the first semiconductor layer; and a plurality of transistor cells each coupled to a source node. The first semiconductor layer includes a plurality of mesa regions each formed between two neighboring ones of the trenches, in each of the mesa regions, at least one of the plurality of transistor cells is at least partially integrated, each of the transistor cells is connected to the source node via a respective source contact, and each of the source contacts is arranged in a respective one of the trenches and is spaced apart from a bottom of the respective trench.

In an entire intermediate region between an active region and an edge termination region, a p.sup.+-type region is provided between a p-type base region and a parallel pn layer. The p.sup.+-type region is formed concurrently with and in contact with p.sup.+-type regions for mitigating electric field near bottoms of gate trenches. The p.sup.+-type region has portions that face, respectively, n-type regions and p-type regions of a parallel pn layer in a depth direction Z and at the portions, has protrusions that protrude toward the parallel pn layer. N-type current spreading regions extend in the entire intermediate region from the active region and are between the p.sup.+-type region and the parallel pn layer, positioned between protrusions of the p.sup.+-type region. The impurity concentration of the n-type current spreading regions in the gate region is higher than that of those in other regions. Thus, avalanche capability may be enhanced.

A transistor device and a method for forming a transistor device are disclosed. The transistor device includes: a SiC semiconductor body that includes a first semiconductor layer and a second semiconductor layer formed on top of the first semiconductor; a trench structure extending from a first surface of the semiconductor body through the second semiconductor layer into the first semiconductor layer; a drain region arranged in the first semiconductor layer; and a plurality of transistor cells each coupled between the drain region and a source node. The trench structure subdivides the second semiconductor layer into a plurality of mesa regions and includes at least one cavity. At least one of the plurality of transistor cells is at least partially integrated in each of the mesa regions.

A semiconductor device, including a substrate, a deposition layer deposited on the substrate, a semiconductor region selectively provided in the deposition layer, a semiconductor layer provided on the deposition layer and the semiconductor region, a first region and a second region selectively provided in the semiconductor layer, a gate electrode provided on the second region and the semiconductor layer via a gate insulating film, a source electrode in contact with the semiconductor layer and the second region, an interlayer insulating film covering the gate electrode, a drain electrode provided on the substrate, a plating film selectively provided on the source electrode at portions thereof on which the protective film is not provided, and a pin-shaped electrode connected to the plating film via solder. The second region is not formed directly beneath a portion where the plating film, the protective film and the source electrode are in contact with one another.

A semiconductor device of the present invention includes a semiconductor layer, a gate trench that defines a source region of a first conductivity type in the semiconductor layer, a channel region of a second conductivity type of a lower part of the source region, a source trench that passes through the source region and the channel region, an impurity region of the second conductivity type of a bottom part and a side part of the source trench, a source electrode on the semiconductor layer, and a highly-concentrated impurity region of the second conductivity type, the highly-concentrated impurity region having a contact portion connected to the source electrode at a surface of the semiconductor layer, the highly-concentrated impurity region passing through the source region and extending to a position deeper than the source region, the highly-concentrated impurity region having a concentration higher than the impurity region.

Disclosed is a bipolar semiconductor device, comprising a semiconductor body having a first surface; and a base region of a first doping type and a first emitter region in the semiconductor body, wherein the first emitter region adjoins the first surface and comprises a plurality of first type emitter regions of a second doping type complementary to the first doping type, a plurality of second type emitter regions of the second doping type, a plurality of third type emitter regions of the first doping type, and a recombination region comprising recombination centers, wherein the first type emitter regions and the second type emitter regions extend from the first surface into the semiconductor body, wherein the first type emitter regions have a higher doping concentration and extend deeper into the semiconductor body from the first surface than the second type emitter regions, wherein the third type emitter regions adjoin the first type emitter regions and the second type emitter regions, and wherein the recombination region is located at least in the first type emitter regions and the third type emitter regions.

According to one embodiment, a semiconductor device includes first to fourth semiconductor regions, first and second electrodes, and a first insulating film. The first semiconductor region includes first and second partial regions, and an intermediate partial region. The first electrode is separated from the first partial region. The second electrode includes first and second conductive regions. The second semiconductor region is provided between the first conductive region and the first electrode. The third semiconductor region is provided between the first conductive region and at least a portion of the second semiconductor region. The fourth semiconductor region includes third and fourth partial regions. The fourth partial region is positioned between the first conductive region and the first electrode. The first insulating film is provided, between the fourth partial region and the first electrode, and between the second semiconductor region and the first electrode.

A method for forming a semiconductor device includes: forming a trench structure with trenches in an inner region and an edge region of a SiC semiconductor body such that the trench structure extends from a first surface of the semiconductor body through a second semiconductor layer into a first semiconductor layer and such that the trench structure, in the second semiconductor layer, forms mesa regions; and forming at least one transistor cell at least partially in each of the mesa regions in the inner region. Forming each transistor cell includes forming at least one compensation region. Forming the compensation region includes implanting dopant atoms of a second doping type via sidewalls of the trenches into the mesa regions in the inner region. Forming the compensation region in each mesa region in the inner region includes at least partially covering the edge region with an implantation mask.

First p.sup.+-type regions are provided directly beneath trenches, separate from a p-type base region and facing bottoms of the trenches in a depth direction. The first p.sup.+-type regions are exposed at the bottoms of the trenches and are in contact with a gate insulating film at the bottoms of the trenches. Second p.sup.+-type regions are each provided between (mesa region) adjacent trenches, separate from the first p.sup.+-type regions and the trenches. Drain-side edges of the second p.sup.+-type regions are positioned closer to a source side than are drain-side edges of the first p.sup.+-type regions. In each mesa region, an n.sup.+-type region is provided separate from the first p.sup.+-type regions and the trenches. The n.sup.+-type regions are adjacent to and face the second p.sup.+-type regions in the depth direction.

A method comprising the irradiation of a wafer by an ion beam that passes through an implantation filter. The wafer is heated to a temperature of more than 200° C. The wafer is a semiconductor wafer including SiC, and the ion beam includes aluminum ions.