A semiconductor device that includes a semiconductor substrate having a first main surface and a second main surface that face each other in a thickness direction, the first main surface containing a trench; an insulation layer on a surface of the trench; a first electrode layer on the insulation layer; a first dielectric layer on the first electrode layer; and a second electrode layer on the first dielectric layer, in which a thickness (L.sub.1) of the insulation layer, a thickness (L.sub.2) of the first electrode layer, and a thickness (L.sub.4) of the second electrode layer satisfy L.sub.1>L.sub.2>L.sub.4.

A semiconductor device includes a first semiconductor substrate, a first insulating film provided at the first semiconductor substrate and including a first recess portion on a surface portion thereof, a first metal film provided at the first recess portion and having a first surface exposed from the first insulating film, a second semiconductor substrate, a second insulating film provided at the second semiconductor substrate and including a second recess portion on a surface portion thereof, a second metal film provided at the second recess portion and having a second surface exposed from the second insulating film, first anti-diffusion films, and second anti-diffusion films provided at outer circumferential portions of the first anti-diffusion films. The second surface is joined to the first surface. The first anti-diffusion films are provided at the first recess portion and the second recess portion and cover the first metal film and the second metal film.

A technique relates to forming a self-aligning field effect transistor. A starting punch through stopper comprising a substrate having a plurality of fins patterned thereon, an n-type field effect transistor (NFET) region, a p-type field effect transistor (PFET) region, and a center region having a boundary defect at the interface of the NFET region and the PFET region is first provided. The field effect transistor is then masked to mask the NFET region and the PFET region such that the center region is exposed. A center boundary region is then formed by etching the center region to remove the boundary defect.

An array substrate and manufacturing method thereof, display panel and display device. The manufacturing method of the array substrate includes: forming, on a substrate, a first conductive pattern, a second conductive pattern and an insulating pattern, the insulating pattern at least covering an upper surface of the first conducting pattern, the first conductive pattern including a first amorphous transparent conductive pattern and a first metal pattern, and the second conductive pattern including a second amorphous transparent conductive pattern; and performing an annealing treatment to convert the first amorphous transparent conductive pattern and the second amorphous transparent conductive pattern to a first crystalline transparent conductive pattern and a second crystalline transparent conductive pattern respectively. The method addresses the problem in which a metal surface is readily oxidizable when performing an annealing treatment, thereby improving the product yield.

Quantum dots and methods of making quantum dots are provided.

A method of positioning elements or additional technological levels on the incident surface of an infrared detector of hybridized type, said detector being formed of a detection circuit comprising an array network of photosensitive sites for the wavelength ranges of interest, hybridized on a read circuit, said detection circuit resulting from the epitaxial growth of a detection material on a substrate, comprising forming within the detection circuit indexing patterns by marking of the growth substrate.