A substrate bonding apparatus for bonding a first substrate to a second substrate includes a first bonding chuck supporting the first substrate, a second bonding chuck disposed above the first bonding chuck and supporting the second substrate, a resonant frequency detector detecting a resonant frequency of a bonded structure with the first substrate and the second substrate which are at least partially bonded to each other, and a controller controlling a distance between the first bonding chuck and the second bonding chuck according to the detected resonant frequency of the bonded structure.

Embodiments provide a method for fabricating a semiconductor device and the semiconductor device. The method includes: providing a semiconductor substrate having a first region and a second region; forming an initial mask layer on an upper surface of the substrate; patterning the initial mask layer, forming a first pattern mask having a first height on the first region, and forming a second pattern mask having a second height on the second region, where a pattern density of the first pattern mask is greater than a pattern density of the second pattern mask, and the first height is greater than the second height; and etching the substrate based on the first pattern mask and the second pattern mask, transferring a pattern of the first pattern mask to the first region, and transferring a pattern of the second pattern mask to the second region.

An integrated circuit includes a resistive material layer formed on a substrate, a metal layer formed on the resistive material layer, a bipolar transistor formed on the substrate, and a resistive element formed on the substrate. The bipolar transistor includes, as a sub-layer, the metal layer formed in a first region, and also includes a collector layer formed on the sub-collector layer. The resistive element is constituted by the resistive material layer formed in a second region.

A nitride semiconductor template includes a heterogeneous substrate, a first nitride semiconductor layer that is formed on one surface of the heterogeneous substrate, includes a nitride semiconductor and has an in-plane thickness variation of not more than 4.0%, and a second nitride semiconductor layer that is formed on an annular region including an outer periphery of an other surface of the heterogeneous substrate, includes the nitride semiconductor and has a thickness of not less than 1 μm.

A nitride semiconductor template includes a heterogeneous substrate, a first nitride semiconductor layer that is formed on one surface of the heterogeneous substrate, includes a nitride semiconductor and has an in-plane thickness variation of not more than 4.0%, and a second nitride semiconductor layer that is formed on an annular region including an outer periphery of an other surface of the heterogeneous substrate, includes the nitride semiconductor and has a thickness of not less than 1 μm.

A method of fabricating a semiconductor device includes implanting dopants into a silicon substrate, and performing a thermal anneal process that activates the implanted dopants. In response to activating the implanted dopants, a layer of ultra-thin single-crystal silicon is formed in a portion of the silicon substrate. The method further includes performing a heteroepitaxy process to grow a semiconductor material from the layer of ultra-thin single-crystal silicon.

An apparatus includes a first and second stages. The first and second stages respectively hold a first and second substrates. The second stage being opposed to the first stage. A stress application portion applies a stress to the first substrate based on a first magnification value. A calculator calculates the first magnification value based on a flatness of the first substrate and a first equation. The first equation represents a relation between flatness of a third substrate, a second magnification value, and an amount of pattern misalignment between the third substrate and a fourth substrate bonded to the third substrate. A controller controls the stress application portion to apply a stress to the first substrate on the first stage based on the first magnification value while the first and second substrates are bonded to each other.

A method for manufacturing an epitaxial wafer by forming a single crystal silicon layer on a wafer containing a group IV element including silicon, the method including the steps of: removing a natural oxide film on a surface of the wafer containing the group IV element including silicon in an atmosphere containing hydrogen; forming an oxygen atomic layer by oxidizing the wafer after removing the natural oxide film; and forming a single crystal silicon by epitaxial growth on the surface of the wafer after forming the oxygen atomic layer, where a planar density of oxygen in the oxygen atomic layer is set to 4×10.sup.14 atoms/cm.sup.2 or less. A method for manufacturing an epitaxial wafer having an epitaxial layer of good-quality single crystal silicon while also allowing the introduction of an oxygen atomic layer in an epitaxial layer stably and simply.

A method for transferring a thin layer onto a destination substrate having a face with an adhesive layer includes formation of a polymer material interface layer on a second face of a thin layer, opposite a first face on which an adhesive is present. The method also includes assembly by gluing the interface layer and the adhesive layer and separation of the thin layer relative to a temporary support.

The present disclosure provides a method of manufacturing a semiconductor structure and a semiconductor structure. The method of manufacturing the semiconductor structure includes: providing an initial structure, where the initial structure includes a laminated structure and a plurality of capacitor holes formed in the laminated structure, and a bottom electrode is formed in each of the capacitor holes; forming a hard mask layer, where the hard mask layer covers a top surface of the initial structure; and partially etching the hard mask layer through an etching gas, to form a plurality of first opening, where the etching gas includes a first gas, and the first gas includes a nitrogen atomic-containing and/or hydrogen atomic-containing gas, to avoid a combination reaction between the first gas and a material of the bottom electrode.