A wafer includes a semiconductor substrate. The semiconductor substrate includes a plurality of first doped regions and a plurality of second doped regions. The first doped regions and the second doped regions are located on a first surface of the semiconductor substrate. The second doped regions contact the first doped regions. The first doped regions and the second doped regions are alternately arranged. Both of the first doped regions and the second doped regions include a plurality of N-type dopants. The doping concentration of the N-type dopants in each of the first doped regions is not greater than the doping concentration of the N-type dopants in each of the second doped regions.

A semiconductor device according to the present disclosure includes a semiconductor substrate having an effective region and an ineffective region, an upper surface electrode layer provided on an upper surface of the semiconductor substrate and a rear surface electrode layer provided on a rear surface of the semiconductor substrate, wherein the semiconductor substrate includes a lifetime control layer that is provided in the effective region, a measurement layer provided at an upper surface side of the ineffective region and a crystal defect layer that is provided in the ineffective region, the upper surface electrode layer includes a plurality of measurement electrodes provided on the measurement layer, the measurement layer includes a conducting layer at least at a portion where the plurality of measurement electrodes are provided, and the crystal defect layer is provided between the plurality of measurement electrodes.

A semiconductor device according to the present disclosure includes a semiconductor substrate having an effective region and an ineffective region, an upper surface electrode layer provided on an upper surface of the semiconductor substrate and a rear surface electrode layer provided on a rear surface of the semiconductor substrate, wherein the semiconductor substrate includes a lifetime control layer that is provided in the effective region, a measurement layer provided at an upper surface side of the ineffective region and a crystal defect layer that is provided in the ineffective region, the upper surface electrode layer includes a plurality of measurement electrodes provided on the measurement layer, the measurement layer includes a conducting layer at least at a portion where the plurality of measurement electrodes are provided, and the crystal defect layer is provided between the plurality of measurement electrodes.

A wafer includes a semiconductor substrate. The semiconductor substrate includes a plurality of first doped regions and a plurality of second doped regions. The first doped regions and the second doped regions are located on a first surface of the semiconductor substrate. The second doped regions contact the first doped regions. The first doped regions and the second doped regions are alternately arranged. Both of the first doped regions and the second doped regions include a plurality of N-type dopants. The doping concentration of the N-type dopants in each of the first doped regions is not greater than the doping concentration of the N-type dopants in each of the second doped regions.